JPH0243606A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make it hard for a generation voltage to receive the fluctuation of a manufacturing process with a low energy consumption by providing first - third MOS transistors at a voltage generating circuit. CONSTITUTION:MOS transistors Q3-Q5, when the potential difference between a gate electrode and a source electrode becomes a threshold voltage Vth or above of respective MOS transistors, becomes the conducting condition. At this time, since the resistance value at the conducting condition of an MOS transistor Q4 is made into a sufficient small value, the potential difference between an output edge O and a connecting point A becomes a threshold voltage Vth4 of a p-channel MOS transistor Q4. The output edge O generates the constant voltage. A resistance value R50 is sufficiently smaller than a resistance value R30 and the generated constant voltage is designed to be a little larger than the Vth4. Since the gate length and the gate width of the p-channel MOS transistor Q4 is sufficiently larger than the gate length and gate width of other MOS transistors Q3 and Q5, it is hard to receive the fluctuation of the manufacturing process and the threshold voltage is stable.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device equipped with a voltage generating circuit that is not easily affected by variations in manufacturing processes or variations in external power supply.

Conventional technology In recent years, in order to miniaturize elements and reduce power consumption in large-capacity dynamic RAM, etc., a method has become popular in which a voltage from an external source is reduced by using a step-down circuit formed inside a semiconductor. However, in this case, there is a need for a circuit that consumes low current, is less affected by fluctuations in the manufacturing process, is less affected by fluctuations in the external power supply, and can be highly integrated.

Hereinafter, a conventional voltage generating circuit incorporated in a semiconductor integrated circuit device will be explained with reference to FIGS. 2 and 3.

FIG. 2 is a circuit diagram showing an example of a conventional voltage generating circuit. In Figure 2, VOO is a positive potential power supply or its power supply voltage, VSS is a power supply with potential Ov, and R1 is the power supply VDD.
A resistor R2 is inserted between the output terminal O and the power supply VSS.

In the voltage generating circuit configured as described above, when the power is turned on, a voltage of R2/(R1+R2)XVDD is generated from the output terminal ○.

FIG. 3 is a circuit diagram showing an example of another conventional voltage generating circuit. In FIG. 3, Ql is a MOS transistor inserted between the power supply VDD and the output terminal O, and Q2 is a MOS transistor inserted between the output terminal O and the power supply VSS.

The operation of the voltage generating circuit configured as described above will be explained below.

When the power is turned on, the output terminal O outputs a potential of (R3+R4)/R4XVDD, assuming that the resistance value of the MOS transistor Q1 is R3 and the resistance value of the MOS transistor Q2 is R4.

Problem to be Solved by the Invention In the case of Figure 2, if you try to reduce the power consumption of the circuit, you will have to increase the value of resistor R1, but
Increasing the value of 1 requires a large area to form a resistor on a semiconductor substrate, which is disadvantageous in terms of miniaturization of integrated circuits.

Furthermore, as shown in Fig. 3, when the resistance value of the MOS transistor is used, it is superior to the structure shown in Fig. 2 in terms of circuit miniaturization, but due to variations in the manufacturing process, each MOS transistor Q + , the resistance value of Q2 changes, making it impossible to generate the expected constant voltage.

Furthermore, both the circuits shown in Figures 2 and 3 are circuits that divide the external power supply according to the resistance ratio and generate a constant voltage, so if the external power supply fluctuates, the generated constant voltage will also change. It had drawbacks.

The present invention solves the above-mentioned conventional problems.The present invention has low power consumption, the generated voltage is resistant to fluctuations in the manufacturing process, and is also resistant to fluctuations in the external power supply. An object of the present invention is to provide a semiconductor integrated circuit device including a voltage generating circuit with a small area.

Means for Solving the Problems The present invention solves the above-mentioned problems by first
A first MOS transistor whose source is connected to the output terminal, a second MOS transistor whose gate and drain are commonly connected and whose drain is connected to the output terminal, and whose source is connected to the second power supply. , the drain is connected to the second MO
This is a semiconductor integrated circuit device including a voltage generating circuit including a third MOS transistor connected to the source of an S transistor.

According to the present invention, the voltage output from the output terminal of the voltage generating circuit is almost controlled by the threshold voltage of the second MOS transistor by designing the gate length and gate width to be large. Therefore, the voltage at the output terminal is
Less susceptible to fluctuations in the manufacturing process and fluctuations in external power supply. Further, in the present invention, since the step-down voltage is generated using the resistance value of the MOS transistor, the area occupied on the semiconductor substrate can be reduced, and the first MOS transistor
) By increasing the resistance value of the transistor, it is also possible to reduce power consumption.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In FIG. 1, VDD is a power supply with a positive potential, VSS is a power supply with a potential Ov, Q3 is an n-channel MOS transistor whose gate is connected to the power supply VSS, and whose drain and source are connected to the power supply VOO and the output terminal ○, respectively. Q4 is an n-channel MOS transistor whose drain and source are connected to the output terminal O and connection point A, respectively, and whose source and gate are commonly connected. Qs is an n-channel MOS transistor whose gate is connected to the power supply vDD, and whose source and drain are connected to connection point A and It is an n-channel MOS transistor connected to power supply VSS. In addition, MOS
The current driving ability of transistor Q5 is larger than that of MOS transistor Q3, and the current driving ability of transistor Q5 is larger than that of MOS transistor Q3.
The current driving capability of MOS transistor Q5 is designed to be larger than that of MOS transistor Q5.

The operation of this embodiment configured as above will be described below.

MOS transistors Q3, Q4 and Qs each have a potential difference between their gate electrode and source electrode (MOS transistor Q3).
, Q4 and Qs become conductive when their threshold voltages vth or higher are reached. Since the resistance value of the MOS transistor Q4 in the conductive state is set to a sufficiently small value, the potential difference between the output terminal 0 and the connection point A becomes the threshold voltage Vth4 of the p-channel MOS transistor Q4. Also, the resistance value of p-channel MOS transistor RO 3 is set to R30゜n.
If the resistance value of channel MOS transistor R5 is R50, the output terminal O is Rso/(R30+R50)×
A constant voltage of (vDD-Vth4)+Vth4 is generated. Note that the resistance value Rso is designed to be sufficiently smaller than the resistance value R30, and the constant voltage generated is designed to be slightly larger than V th4.

The gate length and gate width of p-channel MOS transistor Q4 are sufficiently thick compared to the gate length and gate width of other MOS transistors Q3 and Q5. Threshold voltage Vt
h4 is very stable. Therefore, due to variations in the manufacturing process, MOS transistor Q3. Even if the resistance value of Qs changes, the potential at output terminal 0 does not change much. Further, since the threshold voltage Vth4 of the MOS transistor Q4 has no voltage dependence, the potential at the output terminal O is hardly affected by fluctuations in the power supply VDD.

In addition, in this example, since the resistance value of the MOS transistor is used, even when this circuit is integrated into a semiconductor circuit, the area occupied on the semiconductor substrate can be reduced, and the M
Since the resistance value of the transistor Q3 (OS) is designed to be large, the current consumption is small.

In addition, in the description of the above embodiment, the MOS transistor Q3
, Q4 is singular, but it goes without saying that each MOS transistor may be formed by a plurality of MOS transistors wired in series.

Effects of the Invention The present invention comprises a first MOS transistor whose drain is connected to a first power source and whose source is connected to an output terminal, and a second MOS transistor whose gate and drain are commonly connected and whose drain is connected to the output terminal.
Since the voltage generation circuit is composed of the MOS transistor and the third MOS transistor whose source is connected to the second power supply and whose drain is connected to the source of the second MOS transistor, the generated voltage can be reduced with low power consumption. is less susceptible to fluctuations in the manufacturing process, and less susceptible to fluctuations in the external power supply.
Moreover, when implemented as a semiconductor integrated circuit, it is possible to realize a semiconductor integrated circuit device having a constant voltage generating circuit that occupies a small area on a semiconductor substrate.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention. FIG. 3 is a circuit diagram of a conventional voltage generating circuit. vDD...Positive potential power supply, VSS...
Power supply with potential Ov, R+, R2...Resistance,
Q+, Q2, Q3Q4, Qs...MO
S) Ranjistor. Name of agent: Patent attorney Shigetaka Awano and one other person

Claims (4)

[Claims] (1) A first MOS transistor whose drain is connected to the first power supply and whose source is connected to the output terminal, and a second MOS transistor whose gate and drain are commonly connected and whose drain is connected to the output terminal.
A voltage generating circuit including a transistor and a third MOS transistor having a source connected to a second power source, a drain connected to the source of the second MOS transistor, and a gate connected to the first power source. A semiconductor integrated circuit device characterized by: (2) The current drive capability of the third MOS transistor is the first
The current drive capacity of the MOS transistor is larger than that of the second
The current driving capability of the MOS transistor is the third M
2. The semiconductor integrated circuit device according to claim 1, wherein the current driving capability is larger than that of an OS transistor. (3) The gate length and gate width of the second MOS transistor whose source and gate are commonly connected are the same as those of the first and third MOS transistors.
3. The semiconductor integrated circuit device according to claim 1, wherein the gate length and gate width are sufficiently larger than the gate length and gate width of the S transistor. (4) The first MOS transistor, the third MOS transistor, or both MOS transistors,
4. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed by a plurality of MOS transistors connected in series.