JPH0243621A - Elastic storing - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution by making a word constitution variable when writing and reading are performed. CONSTITUTION:Based on the control information, a writing control means 101 selects a storing means 111 to execute the writing and respective bits of the input data are written into the selected storing means 111. A reading control means 102 selects the storing means 111 to execute the reading in the same manner and the bit information of one bit is respectively read from the selected storing means 111. In accordance with the bit constitution of the input data, the writing and reading actions to plural storing areas 111 are independently controlled. Thus, without using an external circuit, a memory system with a large capacity can be realized.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples ■, Correspondence between the Examples and FIG. 1 ■ , Configuration of the embodiment (i) Configuration of the BS (ii) Detailed configuration of the write control circuit (iii) Detailed configuration of the successive control circuit ■, Operation of the embodiment (i) When the input data is 1 bit (ii) Input When the data is 2 bits (ii) When the input data is 4 bits■, Memory system to which the embodiment is applied (i) Memory system with a capacity of 2048 words (i) Memory system with a capacity of 1024 words■, Summary of the embodiment■ 1. Effects of the Invention [Summary] Regarding elastic stores, the purpose of this invention is to simplify the external circuit when configuring a memory system using multiple elastic stores, having the same storage address, A writing method in which a plurality of storage means for storing data in bits and a predetermined number of bits of human data are introduced, and write operations for each of the plurality of storage means are independently controlled based on control information regarding the number of bits constituting the human data. The storage device is configured to include a control device and a read control device that independently controls read operations for the plurality of storage devices based on control information.

[Industrial application field]

The present invention relates to an elastic store used for speed conversion of data, and particularly to an elastic store in which the word structure of memory is variable.

[Conventional technology]

Speed conversion processing using elastic store (ES) is
This is done by writing input data into the ES in synchronization with the synchronization signal (external clock) and reading out the data stored in the ES in synchronization with the master clock.

FIG. 4 is a configuration diagram of a conventional elastic store.

Four memory cell arrays 402a, 402b.

402c and 402d each have a capacity of 512 bits, and the total capacity is 4 bits x 512 words.

The write address designation unit 403 generates a write address based on the write clock, and the input data latch 401 generates a write address based on the write clock.
Each 1-bit data (data A to D) inputted to a, 401b, 401c, and 401d is stored in the corresponding storage area.

On the other hand, the successive address specifying unit 404 generates successive addresses based on the read clock, reads one bit of data from each of the corresponding storage areas of the memory cell arrays 402a-d, and outputs data latches 405a and 405a.
05b, 40Fyc.

It is temporarily held in 405d and output as 4-bit data.

ES with a capacity of 4 bits x 512 words as described above
is a large-scale integrated circuit (LSI) consisting of a chip. When a memory system with a capacity of 4 bits x 2048 words is configured using this ES, the result is as shown in FIG.

The write control circuit 502 outputs a chip select signal to select, for example, four ESs 501a and 501b.

501c and 501d are selected in order, and input data is written based on the write clock.

The successive output control circuit 503 similarly outputs an output enable signal to sequentially select, for example, the ESs 501a to 501d, and performs reading based on the read clock.

Selector 504 selects ES based on the output enable signal.
The outputs from 501a-d are selected and output as 4-bit data.

[Problems to be Solved by the Invention] By the way, in the above-mentioned conventional method, when increasing the capacity of the memory system by adding ES, it is necessary to
It is necessary to control writing and reading to S.

Therefore, external circuits such as a write control circuit and a read control circuit that generate a chip select signal and an output enable signal are required, resulting in a problem that the circuit becomes complicated.

The present invention was created in view of these points, and an object of the present invention is to provide an elastic store with a simplified circuit configuration.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the elastic store of the present invention.

In the figure, a plurality of storage means 111 have the same storage address and store data in bit units.

The write control means 101 receives input data of a predetermined number of bits, and independently controls write operations to the plurality of storage means 111 based on control information regarding the number of constituent bits of the input data.

The succession control means 102 independently controls read operations for the plurality of storage means 111 based on the control information.

[For production]

Based on the control information, the write control means 101 selects the storage means 111 to perform writing, and writes the selected storage means 11.
Write each bit of input data to 1.

Further, the successive output control means 102 similarly selects the storage means 111 to be read, and reads out one bit of bit information from each of the selected storage means 111.

In the present invention, write and read operations for a plurality of storage areas 111 are independently controlled according to the bit configuration of input data.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an elastic store according to an embodiment of the present invention.

(2) Correspondence between the example and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The write control means 101 corresponds to the write control circuit 210.

The successive output control means 102 corresponds to the successive output control circuit 230.

Storage means 111 corresponds to memory cell array 204.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

In FIG. 2, there are 512 ESs (
Memory cell array 20 having 8×16) memory cells
4a, 204b, 204c, and 204d, a write control circuit 210 that controls write operations to the memory cell arrays 204a to 204d, and a continuation control circuit 230 that controls read operations from the memory cell arrays 204a to 204d. .

ES has four input terminals ■DA to which input data is supplied.
+ ' DI+ I l, Cr I Dfl,
Four output terminals ODA output data read from memory cells.

It has Onm, Ooc, and Oo.

Furthermore, control signals S1 and S2 indicating the number of bits of data input to the ES are supplied to the control input terminals I□, ■, and 2.

In addition, an input data synchronization signal (external clock φ.) is supplied to the write clock terminal (CKw) as a synchronization signal for the write operation, and the read clock terminal (CKr)
The master clock φ is used as the synchronization signal for the read operation.
1 is supplied.

Each memory cell of memory cell arrays 204a-d is O~
The memory cell can be specified by a row address of 15 and a column address of 0 to 7, and write and read operations to the memory cell enable the data line corresponding to the memory cell specified by the row address and column address. It is carried out by

The detailed write control circuit 210 of path ii' is connected to an external clock φ. a frequency dividing circuit 206w that divides the frequency of the frequency dividing circuit 206w, and an address specifying section 22 that generates row addresses and column addresses based on the output of the frequency dividing circuit 206W.
0w and 4-bit latch 2 that temporarily holds input data.
01, and column address selectors 203a, 203b, 203c, which enable the data line indicated by the column address.
203d, selectors 202b, 202c, and 202d that select one of the input data, and a memory cell selection control circuit 205w that outputs a write select signal to control the operation of the column address selector 203axd. .

ES input terminal I FIA+ I Dl+ I I
IC+r DD are input terminals 1a, Ib, and Ic of the launch 201, respectively.

Connected to Id.

The output terminal Oa of the latch 201 is connected to the selector 202b, 2
It is connected to the input terminals 1a of 02c and 202d and the input terminal of the column address selector 203a. Also, latch 2
The output terminal ob of the latch 201 is connected to the input terminal 1b of the selectors 202b and 202d, and the output terminal Oc of the latch 201 is connected to the input terminal 1c of the selectors 202c and 202d.
It is connected to the. In addition, the output terminal Od of the latch 201
is connected to the input terminal Id of the selector 202d.

The memory cell selection control circuit 205w outputs a 1-bit write select signal to each of the column address selectors 203a to 203d.
Supply to a-d.

Here, the column address selectors 203a to 203d do not operate when the write select signal is, for example, "0" and are "1".
is configured to operate when

External clock φ input as a synchronization signal for write operation. are the memory cell selection control circuit 205W and the frequency dividing circuit 2.
06W is supplied.

The addressing section 220 includes an address counter 221 that generates a row address and a column address based on the output of the frequency dividing circuit 206W, a row address latch 222 that temporarily holds a row address, and a column address latch 223 that temporarily holds a column address. , a row decoder 224 that specifies the data line of the row indicated by the row address, and a column decoder 225 that specifies the data line of the column indicated by the column address.

Here, the row address is memory cell array 204a --
d, and the column address is supplied to the column address selector 203.
It is supplied to a-d.

Further, the control signals St and S2 are controlled by the selectors 202b-d,
The signal is supplied to a memory cell selection control circuit 205w and a frequency dividing circuit 206W, respectively.

(ji) Detailed configuration of successive control circuit
Similarly, a frequency dividing circuit 20 that divides the master clock φ1
6r, the address designation section 220r, the column address selectors 207a, 207b, 207c, and 207d, the latch 209 that temporarily holds the read data, and the latch 2
Selectors 208b, 208c, and 208 select one of the input terminals 1a to Id of 09 and input read data.
d and column address selector 2 by the read select signal.
07 Memory cell selection control circuit 205 that controls a-d
It is formed by r.

The output terminals Oa, Ob, Oc, and Od of the latch 209 are E
S output terminal 0DAI ODI+ 06c, 0oEl
It is connected to the.

Further, the output of the column address selector 207a is directly connected to the input terminal 1a of the latch 209.

Further, control signals St, 3
Furthermore, a mask clock φ1 is input to the frequency dividing circuit 206r and the memory cell selection control circuit 205r.
is supplied.

Dan-m41 ES is a control signal 3 indicating the number of bits of input data.
1.32, the number of bits of input data is set to 1.
It is assumed that word storage and read operations are performed.

(i) When the input data is 1 bit For example, 1 bit of serial data from the input terminal IOA among the four input terminals of the ES is the external clock φ. When the input data is input in synchronization with the input data, the control signals S1 and S2 are set to 0'' and 1, respectively, to indicate the number of bits of the input data.

(i-1) The selectors 202b-d select the output from the output terminal Oa of the latch 201 in response to the data write operation control signals 31 and 32.

At this time, data a input to the input terminal InA of ES
are input to all column address selectors 203a-d by selectors 202b-d.

Further, the frequency dividing circuit 206W outputs an external clock φ according to these control signals. is divided into 4 and supplied to the address designation section. Thereby, the address of the memory cell specified by the address specifying section 220w is the external clock φ. It is updated every four cycles.

The memory cell selection control circuit 205W receives control signals 31, S
2, a write select signal for each of column address selectors 203a to 203d is output from an external clock φ. It is set to "1" in turn every cycle of . Thereby, the column address selectors 203a to 203d sequentially select data lines one by one, and output data by validating the data line indicated by the column address.

This causes the external clock φ. input terminal LD in synchronization with
The 4-bit serial data supplied to A is written one bit at a time to four memory cells indicated by the same address in memory cell arrays 204a-d.

(i-2) Data read operation In the same way as the data write operation described above, the frequency dividing circuit 2
6r and the address specifying section 220r, the address of the memory cell to be read is updated every four cycles of the master clock φ1.

Memory cell selection control circuit 205r similarly controls column address selectors 207a-d, whereby bit information is sequentially read out bit by bit from memory cell arrays 204a-d in synchronization with master clock φ.

Control signal S1. In response to S2, the selectors 208b-d each select the input terminal 1a of the latch 209, and input the bit information read from the corresponding memory cell array to the input terminal 1a of the latch 209.

The read data is output as 1-bit serial data from the output terminal Oa of the ES connected to the output terminal Oa of the latch 209.

In this way, the memory cell arrays 204a-
By controlling d, it can be treated as an ES with a capacity of 1 bit x 2048 words.

(ii) If the input data is 2 bits, for example, the external clock φ. When serial data of 1 bit (2 bits in total) is input from each input terminal I□+IDI among the 4 input terminals of the ES in synchronization with the control signal 3.
1. Assume that S2 is set to "1°" and "'0", respectively, to indicate that the input data is 2 bits.

(ii-1) In response to data threshold operation control signals St and S2, selector 202b and selector 202d select data b output from output terminal Ob of latch 201, and selector 202c selects data b output from output terminal Ob of latch 201.
Data a output from output terminal Oa of 01 is selected. As a result, the column address selectors 203a, 203c
Data a is input to column address selector 203b.
, 2()3d receives data b.

Further, the frequency dividing circuit 206W receives an external clock φ according to the control signal Sl, 32. As a result, the address of the memory cell specified by the address specifying section 220w is the external clock φ. It is updated every two cycles.

The memory cell selection control circuit 205w uses an external clock φ to generate write select signals for the column address selectors 203a and 203b and write select signals for the column address selectors 203c and 203d. The column address selectors 203a and 203b and the column address selectors 203c and 203d are controlled to operate alternately by alternately setting them to "1" every cycle.

As a result, data a and data b input to the input terminals Ia and 1b of the latch 201 are transferred to the memory cell array 204.
Data is written alternately to memory cell arrays 204c and 204d.

ii-2) Write data to the frequency dividing circuit 20 in the same way as the data write operation described above.
6r and the address specifying section 220r, the address of the memory cell to be read is updated every two cycles of the master clock φ1.

Similarly, the memory cell selection control circuit 205r controls the column address selectors 207a and 207a by the read select signal.
07b, 207c, and 207d.

As a result, memory cell arrays 204a, b and memory cell arrays 204c, d are synchronized with master clock φ1.
One bit of data (total of two bits) is read out alternately from each of the two bits.

Selector 208b and selector 208 according to the control signal.
d selects the input terminal rb of the latch 209 and inputs data, and the selector 208C selects the input terminal Ia of the latch 209.
Select and do it manually.

As a result, input terminals Ia and Ib of the latch 209 are connected to the memory cell arrays 204a and 204b and the memory cell array 204.
Data read out alternately from c and d is input, and this input data is sent to the ES output terminal ODA+ O□
is output as 2-bit parallel data.

In this way, the memory cell array 204a writes and reads two words of data, with two bits as one word, in four memory cells indicated by the same address.
By controlling -d, it can be treated as an ES with a capacity of 2 x 1024 words.

it) When the card data is 4 bits, 4 bits of parallel data are input to the external clock φ to the input terminals 1 and 1110 of the ES, respectively. When input in synchronization with , both control signals SL and S2 are set to "0",
Indicates that the input data is 4 bits.

(ji-1) Data writing Selectors 202b, 20 according to operation control signals Sl, 32
2c and 202d are output terminals O of the latch 201, respectively.
Data b, data C, and data d output from b, Oc, and Od are selected. Therefore, column address selector 203
Data a % d is input to a to d, respectively.

Control signal 31. In response to S2, the frequency dividing circuit 206W receives the external clock φ. is output as is, and thereby the memory cell array 204a- specified by the address specifying section 220W is outputted as is.
The address of d is the external clock φ. is updated every cycle.

Based on the control signals St and S2, the memory cell selection control circuit 205W sets all write select signals to "1" and operates all column address selectors 203a to 203d.

Therefore, data a to d are each stored in memory cell array 2.
One bit is stored in each memory cell indicated by the same address of 04a-d.

Similar to the write operation of the ij-2 data, the frequency dividing circuit 206r and the address designating section 220r update the address of the memory cell to be read every cycle of the master clock φ.

Similarly, the memory cell selection control circuit 205r operates all column address selectors 207a to 207d simultaneously.

As a result, one bit of each bit (total of 4 bits) of bit information is simultaneously read out from memory cell arrays 204a-d in synchronization with master clock φ1.

In response to control signals 31.32, selectors 208b, 20
8c and 208d are input terminals 1 of the latch 209, respectively.
b, Ic, and Id, and input the bit information read from the corresponding memory cell.

The bit information input to the latch 209 is sent to the output terminal O of the ES in synchronization with the mask clock φ.

~O0 is output as 4-bit parallel data.

In this way, by controlling the memory cell arrays 204a to 204d to write and read data in four memory cells indicated by the same address with 4 bits as one word, an E
It can be treated as S.

As described above, by controlling write operations and read operations for the memory cell arrays 204a-d according to the number of bits of input data, it is possible to vary the number of bits of data that the ES handles as one word.

(2) Memory system to which the example is applied By using a plurality of the above-mentioned ESs, a large-capacity memory system can be constructed.

＜+）Capacity 2048-word memory system Figure 3 (a) shows the memory system (2) using the ES shown in Figure 2.
048 words).

(i-1) Memory system In the diagram, the memory system consists of four ES300a,
It is composed of 300b, 300c, and 300d.

Here, the 4-bit parallel input data (data a, data b, data C, data d) are each ES300
It is input to the input terminal tDA among the four input terminals a, 300b, 300c, and 300d.

The ESs 300a to 300d also have a control signal Sl.

S2 is input manually, and an external clock φ is used as a synchronization signal for write and read operations. , master clock φ, are respectively supplied.

(i-2) Based on the operation control signals Sl and S2 of the memory system, the ES 300a operates as a 1-bit x 204B word ES, and writes data a out of 4-bit parallel manual data (data a to d). Used for reading.

Further, the ESs 300b to 300d are similarly used for writing and reading data b, data C, and data d among input data, respectively.

By operating the ES300a-d in parallel, the external clock φ. Input data of 1 bit (total 4 bits) can be written in synchronization with the master clock φ1, and can be read out in synchronization with the master clock φ1, making it possible to operate as a memory system with an overall capacity of 4 bits x 2048 words. can.

(ii) Memory system with a capacity of 11024 words (Figure 3)
b) is a memory system using ES shown in Figure 2 (
1024 words).

(ii-1) In the configuration diagram of the memory system, the memory system includes two ES300a,
The tail consists of 300b.

Of the data input as 4-bit parallel data (data mill data d), data a and data b are
Among the four input terminals of 300a, input terminal 1 oa,
Input to IDI. Furthermore, data C and data d are input to the input terminal 111A and IDI of the ES 300b.

Furthermore, the ESs 300a and 300b are provided with control signals SL and S2 and an external clock φ, as in the first embodiment described above.

, master clock φ, are supplied.

(ii-2) Based on the memory system operation control signals Sl and S2, the ES300a operates as a 2-bit x 1024-word elastic store, and stores data a,
Used for writing and reading data b.

Similarly, the ES300b inputs data C,
Used for writing and reading data d.

By operating these two ES300a and 300b in parallel, it is possible to write 2 bits each (4 bits in total) of manual data in synchronization with the external clock φ0 and read it out in synchronization with the master clock φ1. 4
It can be operated as a memory system with a capacity of 1024 bits x 1024 words.

V, 14fi(γ(9) As described above, the four memory cell arrays 204a, 204b, 204c, 20
Write operations and read operations for 4d are independently controlled.

This allows the number of bits constituting one word of data handled by the ES to be variable, such as 1 bit, 2 bits, or 4 bits.

By applying such ES, Figure 3 (a),
As shown in (b), a large capacity memory system using a plurality of ESs can be realized without adding an external circuit.

(1) Form of one-shot H In the above-described embodiment of the present invention, an ES having four memory cell arrays has been described, but there is no limit to the number of memory cell arrays or the number of bits of input data.

In addition, in r(, Correspondence between Examples and FIG. 1),
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, a memory system with a large capacity can be realized without using an external circuit by making the word structure variable when writing and reading data in an elastic store, which is practical. is extremely useful.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the elastic store of the present invention, Figure 2 is a configuration diagram of the elastic store of an embodiment of the present invention, and Figure 3 is a memory system using the elastic store shown in Figure 2. FIG. 4 is a configuration diagram of a conventional elastic store, and FIG. 5 is a configuration diagram of a conventional memory system. In the figure, 101 is a write control means, 102 is a continuation control means, 111 is a storage means, and 300.501 is an elastic store (ES) 201.
．． 209 is a latch, 202.208 is a selector, 203.207 is a column address selector, 204.402
is a memory cell array, 205 is a memory cell selection control circuit, 206 is a frequency dividing circuit, 210 is a write control circuit, 220 is an addressing section, 221 is an address counter, 222 is a row address latch, 223 is a column address latch, 224 is a 225 is a column decoder, 230 is a continuation control circuit, 401 is an input data latch, 3 is a write address designation section, 4 is a continuation address designation section, 5 is an output data latch, 2 is a write control circuit, 3 is a In the successive control circuit, 4 is a selector. S, frr"-'? O, Tribe sail door construction 7"D"y diagram Figure 1

Claims (1)

[Claims] (1) A plurality of storage means (111) having the same storage address and storing data in bit units and input data of a predetermined number of bits are introduced, and based on control information regarding the number of constituent bits of the input data, The plurality of storage means (1
write control means (101) for independently controlling write operations for the plurality of storage means (111) based on the control information;
) readout control means (102) for independently controlling readout operations for each of the elastic stores.