JPH024363U

JPH024363U -

Info

Publication number: JPH024363U
Application number: JP8198788U
Authority: JP
Priority date: 1988-06-21
Filing date: 1988-06-21
Publication date: 1990-01-11

Description

[Brief explanation of drawings]

第１図は本考案の実施例を示すブロツク線図、
第２図は本考案を適用して好適な静止画通信端末
の一例を示すブロツク線図である。２は同期分離回路、３は位相比較器、４は第１
のスイツチ、５はローパスフイルタ、６は可変発
振器、７は水平同期分周回路、９は第２のスイツ
チ、１０は垂直同期分周回路、１２はＰＬＬ回路
である。 FIG. 1 is a block diagram showing an embodiment of the present invention;
FIG. 2 is a block diagram showing an example of a still image communication terminal suitable for applying the present invention. 2 is a synchronous separation circuit, 3 is a phase comparator, and 4 is a first
5 is a low-pass filter, 6 is a variable oscillator, 7 is a horizontal synchronous frequency divider circuit, 9 is a second switch, 10 is a vertical synchronous frequency divider circuit, and 12 is a PLL circuit.

Claims

[Claims for Utility Model Registration] A phase comparator, a low-pass filter to which the output of the phase comparator is supplied through a first switch, and a variable oscillator to which the output of the low-pass filter is supplied and whose oscillation frequency is controlled. A clock signal from the variable oscillator of the PLL circuit is supplied to the PLL circuit, a second switch, and the frequency is divided, and an external horizontal synchronization signal is supplied as a clear signal through the second switch to perform internal horizontal synchronization. a frequency divider circuit from which a signal is output, the external horizontal synchronization signal and the internal horizontal synchronization signal from the frequency divider circuit are supplied to a phase comparator of the PLL circuit for phase comparison, and a video display. During the period, the first switch is turned on and the second switch is turned off. During the period other than the video display period, the first switch is turned off and the second switch is turned off. A synchronous circuit that is turned on.