JPH0243769A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve a bonding in reliability, to form a pad metal layer accurately into steps at the manufacture of a device, and to enable the formation of a conductive layer at a time with an electrode layer of the semiconductor device by a method wherein a first conductive layer is formed on a semiconductor substrate and a bonding pad layer is formed thereon. CONSTITUTION:A first conductive layer 23 is formed on a semiconductor substrate 21, and a bonding pad layer 25 is formed thereon. For instance, an N-type action layer 22 is formed on a GaAs substrate 21 through an ion implantation method or the like, then the conductive layer 23 is formed through a sputtering method, and then the conductive layer 23 is processed through an ion milling method or the like to be formed into a gate metal 231 and a first pad metal 232. Here, the conductive layer 23 is, for instance, composed of a Ti layer as a lowermost layer, an Mo layer as a second layer, and a Au layer as a third layer. The Ti layer and the Mo layer serve as a barrier against Ga diffusion of the substrate 21. Thereafter, an ohmic metal layer 24 is formed through a lift-off method, and then a second pad metal layer 25 is formed on the first pad metal 232 through a lift-off method to obtain a high frequency GaAs FET.

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention (Field of Industrial Application) The present invention relates to a semiconductor device with an improved semiconductor f4 node and a method for manufacturing the same. It is used in high frequency GaAs FETs.

(Prior Art) At present, in this high-frequency GaAs FET l/i, sanding is directly formed on a semiconductor substrate by a lift-off method.

FIG. 2 shows this method. As shown in FIG. 2(a), a semi-insulating undoped GmAm substrate 11 is covered with an N-type active layer (
N-type 4-layer 1g) 12 is formed, then dart metal 13 and ohmic metal 4 are formed separately as shown in Fig. 2(b), and then 7 to 7 is formed as shown in Fig. 2(c). Apply Lesostono 5. After forming a layered pad metal layer 16 for a long time, unnecessary parts of layers 15 and 16 were removed using the 7-to-7 method, thereby forming a base metal layer 16 as shown in Fig. 2(d). do.

(Problem to be Solved by the Invention) Currently, products that have been commercialized are formed by directly forming the Good Metal No. 16 on the semiconductor substrate by the lift-off method, as described above, but this There were problems with the process and the assembly process was hindered.

This is because, if the thickness of the bonding non-contact layer 16 is small, the GaAs substrate 11 will be brittle and cracks will easily occur during bonding with Au wires and the like. So Zandingo 9. D)-16 may be made thicker, but then it becomes difficult to cut the part of the layer 16 that needs to be cut during the lift-off process shown in Fig. 2 (C), and this defect occurs. , it becomes impossible to proceed to the subsequent process steps and assembly steps.

In addition, the Ga of the GaAs substrate 11 is A
It is easy to diffuse through the U-bond layer 16, and when Ga comes near the surface of the Au-bond j-16, the connection between the laminated layer 16 and the Au wire (not shown) is not well established. Bo/D/G defects are likely to occur.Therefore, AuN7
Although it is possible to remove the Ti layer that serves as a barrier for the KGa under the heating layer 16, this is still insufficient.

The object of the present invention is to improve the reliability of rteying,
Also, during manufacturing, the flat metal layer can be cut correctly, and the new 4't!
The layer can be formed together with a cage of semiconductor elements,
The purpose is to avoid complicating the process.

[Structure of the invention] (Means and effects for solving problem tA) The present invention provides the following features: (a) A first area of 1 m is formed on a semiconductor substrate, and a bonding pad layer is formed on the conductive layer. This is a semiconductor device characterized by the following. The present invention also provides (b) a compound semiconductor that includes the semiconductor substrate dGa, and
In the semiconductor device according to item (a) above, the conductive node is one that forms a barrier to Ga such as Ti, Mo, etc. In addition, the present invention provides the following steps: (c) simultaneously forming an electrode layer for a semiconductor element and a first conductive layer for a bonding pad on a semiconductor substrate, and laminating a bonding pad layer' on the first conductive layer. This is a method of manufacturing a semiconductor device that takes into account the following characteristics. In addition, the present invention has the following features: (2) The cutting semicircular substrate is a compound semiconductor containing Ga, and the first bonding layer formed by forming a barrier layer against Ga such as Ti, +Vto, etc. ( This is the method for manufacturing a semiconductor device according to item c). The present invention also provides a method for manufacturing a semiconductor device according to (c) above, characterized in that (e) the bonding pad layer is formed by a cut-off method.

That is, the present invention prevents the occurrence of substrate cracks by increasing the thickness of all the layers. Furthermore, by using multiple layers as described above, the portion of the bonding pad layer formed by the lift-off method can be formed thinly, so that the pad layer can be properly separated. In addition, a barrier metal against Ga is used on the lower layer side of the multilayer bonding pad to eliminate mending defects. Further, the lower layer of the multilayer and the electrode of the semiconductor element are simultaneously formed to simplify the process.

(Example) An example of the present invention will be described below with reference to the drawings. 'Figure 1 takes a high frequency modified GaAs FET as an example.

First, as shown in FIG. 1(a), an N-type active layer (four N-type layers) 22 is formed on a GaAs substrate 2 using ion-implanted paper or the like. Next, as shown in FIG. 1(b), a conductive layer 23, which will become a dirt metal and a first pad metal, is placed on the substrate 9.
Formed using the tarry/gu method. After that, RIE (Reacti)
As shown in FIG. 1(e), a first metal 2311 and a dome metal 232 are processed and formed by ion etching, ion milling, etc. as shown in FIG. 1(e). Here, an example of the conductive layer 23 (231, 232) is the bottom Ti layer.
The 12th layer is a Mo layer, and the 31st layer is an Au layer. This T
The i-layer, Mo/-, serves as a barrier against Ga diffusion in the substrate 21. Furthermore, use the lift-off method to create an ohm as shown in Figure 1(d).

After forming the metal layer 24, the lift-off method is again used (same as in the case of FIGS. 2(C) and 2(d)), as shown in FIG.
) 9th < 4 layer m (1st 74′ metal) 23□
The upper part forms a second metal shield 25.

In the FET shown in FIG. 1, one metal layer 24 is the source and the other metal layer 24 is the drain. The '1 current flows between the source and drain by controlling the depletion layer by .

If the configuration is as shown in FIG. 1(e), there will be the following advantages. That is, the bonding layer 232.2
The two-layer structure (5) makes it thick, and this serves as a cushion material to absorb shock during wire bonding (9) and prevents circulation of the fragile GaAs substrate (21f). Also, by having two layers of bonding and rad e 232 and 25, the entire yd 232 can be formed to be thin, and therefore the contact layer 23
Step 2: Step cutting can be performed correctly, and wiring can be formed correctly. The conductive layer 232 has a Ti layer and a Mo layer on the lower/l# side, which acts as a barrier against Ga on the substrate 2.
This prevents the wire a from going to the uppermost Au layer of the conductive layer 232, the Au solid metal layer 25, and the Au & ending wire is reliably bonded to the pad layer 25. Also the first
In the process shown in Figure (c), the gate'-pole 23! Since the first pad layer 232 can be formed at the same time, there is no increase in the number of steps compared to the expedited example shown in FIG.

It should be noted that the present invention is not limited to the Vi example, and individual applications are possible. For example, when the semiconductor substrate used in the present invention is made of a compound semiconductor such as GaP, similar effects can be obtained.

[Effects of the invention] As explained above, according to the invention, the reliability at the time of boarding can be reduced by 1q, and the step cutting of the bond metal can be performed correctly during manufacturing, and the layer of the bottom metal layer of the lower TV4 um can be cut by 1q. This method has the advantage that the process is not complicated because it is formed simultaneously with the top and bottom layers of the semiconductor device.

4. Explanation of rII5 ratio of the drawings Fig. 1 is a process diagram of a one-to-7 modification example of the present invention, and Fig. 2 is a process diagram of a conventional device.

2)-GaAs &+Ji,, 23 ・-
41, l? IJ, 23. The gate voltage tm formed by -23, the lower side formed by 232...23 (
Good layer, 25... above) Gu, Do layer.

Claims (5)

[Claims] (1) A semiconductor device characterized in that a first conductive layer is formed on a semiconductor substrate, and a bonding pad layer is formed on the conductive layer. (2) The semiconductor device according to claim 1, wherein the semiconductor substrate is a compound semiconductor containing Ga, and the first conductive layer forms a barrier layer against Ga such as Ti or Mo. (3) A semiconductor device characterized in that an electrode layer for a semiconductor element and a first conductive layer for a bonding pad are simultaneously formed on a semiconductor substrate, and a bonding pad layer is laminated on the first conductive layer. manufacturing method. (4) The method for manufacturing a semiconductor device according to claim 3, wherein the semiconductor substrate is a compound semiconductor containing Ga, and the first conductive layer forms a barrier layer against Ga such as Ti or Mo. (5) The method of manufacturing a semiconductor device according to claim 3, wherein the bonding pad layer is formed by a lift-off method.