JPH0244432A - Electronic computer control system - Google Patents

Abstract

PURPOSE:To detect the mix-up of a return address with data or a register, etc., due to mis-programming by setting the generating/checking mode of redundant information for error detection in the case of the call/return of a subroutine differently from that of push/hop of the data and the register, etc. CONSTITUTION:A parity generation circuit 11 and a parity check circuit 12 are provided with two kinds of redundant information generating/checking modes, and an instruction decoder 10 which outputs a parity control signal 23 performs the generation/checking of the redundant information with the redundant information generating/checking mode on one side at the time of performing the call/return of the subroutine. At the time of performing the push/hop of the data and the register, etc., the generation/checking of the redundant information is performed with the redundant information generating/ checking mode on the other side. In such a manner, it is possible to easily detect the mix-up of the return address with the data or the register due to the mis-programming, etc.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an electronic computer control method, and in particular subroutine call/return and push/return of data, registers, etc.
A computer control method for an electronic computer in which the same stack is used for the pop-up and redundant information for error detection is attached to this stack [Prior art] Conventionally, one stack is used to call/return subroutines ( i.e. push/pop of return address)
In electronic computers that push/pop data, registers, etc. (excluding return addresses; the same applies hereinafter), there is no distinction between return addresses and data, registers, etc. in the stack, and after entering the stack, It was not possible to determine from the contents whether it was a return address, data, register, etc.

[Problem to be solved by the invention]

In the above-mentioned conventional computer control method, errors may occur due to confusion between return addresses and data or registers, such as popping pushed data as a return address or accidentally pumping a pushed return address into a register. The drawback is that programming errors cannot be detected and debugging the program is difficult.

Another drawback is that when analyzing the route taken by the program based on the contents of the stack, it is difficult to distinguish between return addresses and data, registers, etc., making route analysis difficult.

In view of the above-mentioned points, an object of the present invention is to perform subroutine calls/returns and pushes/returns of data, registers, etc.
By changing the generation/checking mode of redundant information for error detection depending on the pop-up case, we have developed an electronic computer control method that can easily detect mistakes in return addresses and data, registers, etc. due to programming errors. It is about providing.

[Means to solve the problem]

The computer control method of the present invention is applicable to an electronic computer in which the same stack is used for calling/returning subroutines and pushing/pumping data, registers, etc., and redundant information for error detection is attached to this stack. , a redundant information generating/checking means with two types of redundant information generating/checking modes, and when calling/returning a subroutine, redundant information is generated/checked in one of the redundant information generating/checking modes, and data, registers, etc. redundant information generating/checking mode control means for controlling the redundant information generating/checking means so that redundant information is generated/checked in the other redundant information generating/checking mode when the redundant information generating/checking mode is pushed/popped.

(Function) In the computer control system of the present invention, the redundant information generation/checking means has two types of redundant information generation/checking modes, and the redundant information generating/checking mode control means is configured to control the redundant information generation/checking mode at the time of subroutine call/return. generates/checks redundant information in redundant information generation/check mode on one side, and generates/checks redundant information on the other side in case of push/pop of data or registers, etc.
The redundant information generating/checking means is controlled so as to perform the following steps.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing the configuration of a computer to which a computer control method according to an embodiment of the present invention is applied. This electronic computer includes a processing device 1, a memory (main memory) 2, an instruction decoder 10 included in the processing device 1,
Its main parts are composed of a parity generation circuit 11, a parity check circuit 12, and a stack 13 provided in the memory 2.

The processing device 1 sends an address 20 and write data 21 to the memory 2, and receives continuous write data 24.

Furthermore, when the processing device 1 receives an interrupt signal 25 for error detection from the parity checker circuit 12, the instruction decoder IO outputs "l" as the parity control signal 23 when decoding an instruction for calling/returning a subroutine. However, it outputs "0" as the parity control signal 23 when decoding an instruction to push/pop data, registers, etc.

The parity generation circuit 11 has a first parity generation mode in which, for example, even parity is generated for the write data 21, and a second parity generation mode in which, for example, odd parity is generated.

The parity check circuit 12 has a first parity check mode in which the read data 24 is checked for, for example, even parity, and a second parity check mode in which, for example, it is checked for odd parity. Furthermore, the parity check circuit 12 generates a "1°" interrupt signal 25 when a parity error is detected.

In the stack 13, parity 22 is stored as redundant information in association with write data 21 consisting of return addresses, data, registers, etc.

Note that the parity generation circuit 11 and the parity check circuit 12 correspond to redundant information generation/check means having two types of redundant information generation/check modes, and the instruction decoder IO that outputs the parity control signal 23 is used for calling/checking subroutines. When returning, redundant information is generated/checked in redundant information generation/check mode on one side, and when data or registers are pushed/popped, redundant information is generated/checked in redundant information generation/check mode on the other side. This corresponds to a redundant information generation/check mode control means that controls the redundant information generation/check means to perform the redundant information generation/check mode.

Next, the operation of the computer control method of this embodiment configured as described above will be explained.

When an instruction to call/return a subroutine is executed in the processing device 1, the instruction decoder 10 outputs "l" as the parity control signal 23, and the parity generation circuit 11 enters the first parity generation mode and outputs the parity 22. The parity check circuit 12 enters the first parity check mode and checks whether the parity 22 included in the read data 24 from the stack 13 is even parity. As a result of this parity check, if the parity 22 is not even parity, the parity check circuit 12 sets the interrupt signal 25 to "1" and notifies the processing device 1 of the detection of a parity error.

On the other hand, when an instruction to push/pop data or registers is executed in the processing unit I, the instruction decoder I
“0” is output from O as the parity control signal 23,
The parity generation circuit 11 enters the second parity generation mode and generates odd parity as the parity 22, and the parity check circuit 12 enters the second parity check mode so that the parity 22 included in the read data 24 from the stack 13 is Check for odd parity. As a result of this parity check, if the parity 22 is not odd parity, the parity check circuit 12 sends an interrupt signal 25
is set to "1" to notify the processing device 1 of the detection of a parity error.

In the above embodiment, an example in which parity is used as redundant information has been described, but redundant information is not limited to parity, and it goes without saying that other redundant information such as a cyclic redundancy check code may be used. Nor.

〔Effect of the invention〕

As explained above, the present invention provides subroutine calls/
By changing the generation/checking mode of redundant information for error detection in the case of a return and in the case of push/pop of data, registers, etc., it is possible to detect mix-ups between return addresses and data, registers, etc. due to programming errors, etc. It has the effect of making it possible.

Additionally, by extracting redundant information when analyzing the contents of the stack, it is possible to distinguish return addresses from data, registers, etc., making it easier to analyze program paths. be.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing the configuration of a computer to which a computer control method according to an embodiment of the present invention is applied. In the figure, these are a processing unit, memory, instruction decoder, parity generation circuit, parity check circuit, stack, address, write data, parity, parity control signal, read data, and interrupt signal.

Claims (1)

[Claims] In an electronic computer in which the same stack is used for calling/returning a subroutine and pushing/popping data, registers, etc., and redundant information for error detection is attached to this stack, two types of redundant information are provided. A redundant information generating/checking means having a generating/checking mode, and one redundant information generating/checking mode generates/checks redundant information when calling/returning a subroutine, and when pushing/popping data or registers, etc. Generate redundant information on the other side / Generate redundant information in check mode /
1. A computer control system comprising redundant information generation/check mode control means for controlling said redundant information generation/check means to perform a check.