JPH0244791U - - Google Patents

Info

Publication number
JPH0244791U
JPH0244791U JP12351088U JP12351088U JPH0244791U JP H0244791 U JPH0244791 U JP H0244791U JP 12351088 U JP12351088 U JP 12351088U JP 12351088 U JP12351088 U JP 12351088U JP H0244791 U JPH0244791 U JP H0244791U
Authority
JP
Japan
Prior art keywords
recording
playback
sequencer
performance event
address pointer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12351088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12351088U priority Critical patent/JPH0244791U/ja
Publication of JPH0244791U publication Critical patent/JPH0244791U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案を適用して構成したデイレイ
トリガー機能付電子楽器の全体回路図、第2図は
録音/マルチデイレイ再生に関連して使用される
レジスタ群を示している図、第3図は録音/マル
チデイレイ再生の動作の流れを示している図、第
4図は演奏イベントについての記録及び再生の動
作例を処理ステツプに対応させて示している図、
第5図は、第4図の各処理ステツプでのバツフア
及びポインタの動きを示している図、第6図及び
第7図は従来技術の説明するための模式図である
。 1……CPU、2……鍵盤部、3……スイツチ
部、5……ROM、6,8……RAM、7……音
源LSI、9……サウンドシステム。
Figure 1 is an overall circuit diagram of an electronic musical instrument with a delay trigger function constructed by applying this invention, Figure 2 is a diagram showing a group of registers used in connection with recording/multi-delay playback, and Figure 3. 4 is a diagram showing the flow of recording/multi-delay playback operations, and FIG. 4 is a diagram showing an example of recording and playback operations for performance events in correspondence with processing steps.
FIG. 5 is a diagram showing the movement of the buffer and pointer at each processing step in FIG. 4, and FIGS. 6 and 7 are schematic diagrams for explaining the prior art. 1... CPU, 2... Keyboard section, 3... Switch section, 5... ROM, 6, 8... RAM, 7... Sound source LSI, 9... Sound system.

Claims (1)

【実用新案登録請求の範囲】 シーケンサメモリと、 このシーケンサメモリに対する録音アクセスご
とに歩進される録音アドレスポインタ手段及び演
奏入力装置における演奏イベントの発生時間情報
を計測する録音タイマー手段を含み、上記演奏入
力装置からの演奏イベントの発生に応答して、そ
の演奏イベントのコード及び上記録音タイマー手
段が示す発生時間情報を、上記録音アドレスポイ
ンタ手段が示す上記シーケンサメモリのエリアに
記録するシーケンサ録音処理手段と、 上記シーケンサメモリに対する再生アクセスご
とに歩進される再生アドレスポインタ手段及び上
記録音タイマー手段より所定時間遅れた値に初期
設定される再生タイマー手段を有し、上記再生ア
ドレスポインタ手段の示す上記シーケンサメモリ
のエリアに記録された演奏イベントの発生時間情
報と上記再生タイマー手段の内容とが一致したと
きに該当する演奏イベントを実行するシーケンサ
再生処理手段と、 上記シーケンサ再生処理手段による演奏イベン
トの実行と共に、その再生された演奏イベントの
コードを上記録音アドレスポインタ手段が示す上
記シーケンサメモリのエリアに記憶させると共に
上記録音タイマー手段の示す時間情報を上記録音
アドレスポインタ手段が示すアドレスの1つ前の
アドレスでのイベントの時間長として記録させる
制御手段と を具備してなるデイレイトリガー機能付電子楽
器。
[Claims for Utility Model Registration] A sequencer memory, a recording address pointer means that is incremented each time a recording access is made to the sequencer memory, and a recording timer means that measures the time information of a performance event in a performance input device. sequencer recording processing means for recording a code of the performance event and occurrence time information indicated by the recording timer means in an area of the sequencer memory indicated by the recording address pointer means in response to the occurrence of a performance event from an input device; , comprising a playback address pointer means that is incremented each time the sequencer memory is accessed for playback, and a playback timer means that is initially set to a value delayed by a predetermined time from the recording timer means, the sequencer memory indicated by the playback address pointer means. sequencer playback processing means for executing the corresponding performance event when the occurrence time information of the performance event recorded in the area matches the content of the playback timer means; and in addition to the execution of the performance event by the sequencer playback processing means; The code of the played performance event is stored in the area of the sequencer memory indicated by the recording address pointer means, and the time information indicated by the recording timer means is stored at the address immediately before the address indicated by the recording address pointer means. An electronic musical instrument with a delay trigger function, comprising a control means for recording the time length of an event.
JP12351088U 1988-09-22 1988-09-22 Pending JPH0244791U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12351088U JPH0244791U (en) 1988-09-22 1988-09-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12351088U JPH0244791U (en) 1988-09-22 1988-09-22

Publications (1)

Publication Number Publication Date
JPH0244791U true JPH0244791U (en) 1990-03-28

Family

ID=31372434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12351088U Pending JPH0244791U (en) 1988-09-22 1988-09-22

Country Status (1)

Country Link
JP (1) JPH0244791U (en)

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