JPH0245434B2 - SUITSUCHINGUDENGENKAIRO - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a switching power supply circuit that prevents the control ability from decreasing due to the inductance not switching in response to changes in the load, and that can supply a stable DC voltage to any load. It is related to.

2. Description of the Related Art Conventionally, a switching power supply circuit as shown in FIG. 1 has been proposed as a switching power supply circuit that can supply a stable DC voltage to any load without reducing efficiency.

That is, in FIG. 1, 1 indicates a power plug to which commercial AC voltage is supplied, and this power plug 1
The commercial AC voltage from is supplied to the rectifier circuit 3 through the power switch 2, where it is rectified and smoothed into DC voltage.
This DC voltage is supplied to the npn transistor 6 constituting the first switching element via the primary coil 4a of the transformer 4 and the reverse current prevention diode 5, and the DC voltage obtained at the intermediate tap of the primary coil 4a is A voltage is supplied to an npn transistor 7 constituting a second switching element.
In this case, the inductance value between one end of the primary coil 4a and the intermediate tap is _L1 , and the primary coil 4a
The inductance value between one end and the other end of a is L ₂
shall be.

Further, an alternating current voltage is taken out to the secondary coil 4b of the transformer 4, which is supplied to a rectifier circuit 8, where it is rectified and smoothed into a direct current voltage, and this direct current voltage is taken out to an output terminal 9. The voltage value of the voltage at this output terminal 9 is detected by a voltage detection circuit 10, and this detection output is supplied as a modulation input to a pulse width modulator 12 that generates a switching signal through a coupler 11 for isolation such as a photocoupler. At the same time, the clock pulse from the clock pulse generator 13 is supplied to this pulse width modulator 12 as its carrier, and the pulse width of the switching signal obtained at the output side of this pulse width modulator 12 is determined by the DC voltage obtained at the output terminal 9. It can be varied to stabilize at a desired constant value.

Furthermore, 20a and 20b indicate first and second reference pulse input terminals, respectively. The first reference pulse supplied to the first reference pulse input terminal 20a changes its pulse width a to the switching signal on the output side of the pulse width modulator 12 when the transistor 7 is used, as shown in FIG. The pulse width is selected to be slightly wider than the value at which the pulse width becomes a light load and the minimum value, and the second reference pulse supplied to the second reference pulse input terminal 20b is the second reference pulse.
As shown in Figure C, when the pulse width b is the duty ratio Da of the first reference pulse and the duty ratio Db of the second reference pulse. It was selected as follows. In this case, the first and second reference pulses are made to be synchronized with the clock pulses of the clock pulse generator 13 shown in FIGS. 2a and 2b. The first reference pulse supplied to the first reference pulse input terminal 20a is supplied to one input terminal of the NAND circuit 21, and a "0" or "1" signal is obtained at the Q output terminal of the flip-flop circuit 17. is supplied to the other input terminal of the NAND circuit 21, the second reference pulse supplied to the second reference pulse input terminal 20b is supplied to one input terminal of the NAND circuit 22, and the Q output of the flip-flop circuit 17 is supplied to the second reference pulse input terminal 20b. The signal obtained at the terminal is supplied to the other input terminal of the NAND circuit 22 through the inverter circuit 23, and the respective output signals of the NAND circuits 21 and 22 are supplied to one input terminal and the other input terminal of the NAND circuit 24, respectively. do. In this case, NAND circuits 21, 22,
and 24 and the inverter circuit 23 constitute a reference pulse selection circuit, and when the output signal of the Q output terminal of the flip-flop circuit 17 is "1", a first reference pulse is obtained on the output side of the NAND circuit 24.
When the output signal of the output terminal is “0”, a second reference pulse is obtained, and the reference pulse of the first reference pulse or the second reference pulse obtained at the output side of the NAND circuit 24 is output to one of the comparison circuits 25. The switching signal, which is the output signal of the pulse width modulator 12, is supplied to one input terminal of the exclusive OR circuit 26, and the flip-flop circuit 1
The “0” or “1” signal obtained at the Q output terminal of 7 is supplied to the other input terminal of this exclusive OR circuit 26, and the output signal of this exclusive OR circuit 26 is applied to the comparison circuit 25. Supplied to the other input terminal. This comparator circuit 25 is configured such that its output side becomes "1" when the output signal of the exclusive OR circuit 26 is a high level signal "1" at the falling edge of the reference pulse. The output signal of the comparison circuit 25 is supplied to the D terminal of the flip-flop circuit 17.

Now, the pulse width of the switching signal of the output signal of the pulse width modulator 12 is wider than the pulse width a of the first reference pulse and narrower than the pulse width b of the second reference pulse, as shown in FIG. If it's heavy,
When the output signal of the Q output terminal of the flip-flop circuit 17 is "1", the switching signal is supplied to the base of the transistor 7 through the AND circuit 19, and this transistor 7 is switched according to the DC output voltage of the output terminal 9. The DC output voltage is kept constant. At this time, the output side of the NAND circuit 24 has the first pulse width a as shown in FIG.
A reference pulse is obtained. Next, when the load on the output terminal 9 becomes lighter and the pulse width of the switching signal of the pulse width modulator 12 becomes narrower than the pulse width a of the first reference pulse as shown in FIG. Since the Q output of the flip-flop circuit 17 is "1" as shown in FIG. 2A, the output signal of the circuit 26 is "1" as shown in FIG. Supplied. Since the first reference pulse shown in FIG. 2A and C is supplied to the other input terminal of the comparison circuit 25, the AND circuit 25a of the comparison circuit 25
(FIG. 2c) gives the output shown in FIG. 2A F. This output (FIG. 2a, F) and the output of the exclusive OR circuit 26 (FIG. 2a, E) are supplied to the exclusive OR circuit 25b (FIG. 2c), and the output is shown in FIG. 2A, G. An output signal is obtained. This output signal is transmitted to the flip-flop circuit 25.
C (FIG. 2c) is inverted, and the output signal of the Q output terminal (H in FIG. 2a) is supplied to the D input terminal of the flip-flop circuit 17, and in synchronization with the clock signal of the clock pulse generation circuit 13, As shown in Figure B, the Q of the flip-flop circuit 17 is
The output signal of the output terminal is set to "0", the output signal of the output terminal is set to "1", the reference pulse obtained at the output side of the NAND circuit 24 is set as the second reference pulse, and the switching signal from the pulse width modulator 12 is ANDed. It is supplied through a circuit 18 to the base of transistor 6 and switches this transistor 6. In this case, since the pulse width of the switching signal on the output side of the pulse width modulator 12 is modulated according to the level of the DC output voltage obtained at the output terminal 9, the DC output voltage obtained at the output terminal 9 is kept constant. I can do that. In this case, since the input DC voltage Vi from the rectifier circuit 3 is supplied to the primary coil 4a of the transformer 4, that is, the entire primary coil having an inductance value _L2 , the period of the second reference pulse is
When T _P is the load size, R _L is the load size, and η ₁ is the efficiency of the transformer 4 and transistor 6, the output DC voltage V ₀
teeth Also, the maximum output power P ₀₁ is P ₀₁ =V ₀ ² /R _L η ₁ =Vi ² ·Db ² ·T _P ·η ₁ /2L ₂ (1). In this case, when the load on the output terminal 9 becomes heavy (when the current flowing through the load becomes large), the output DC voltage decreases accordingly, so the pulse width of the output signal of the pulse width modulator 12 becomes large. When the pulse width b becomes larger than the second reference pulse width b as shown in FIG. 2b (B) is supplied, the switching signal of the pulse width modulator 12 is directly applied to the output of the exclusive OR circuit 26 (Fig. 2b).
E) and is supplied to one input terminal of the comparison circuit 25. Since the Q output of the flip-flop circuit 17 is "0", the other input terminal of the comparison circuit 25 is supplied with the second reference pulse shown in FIG. At the output of the AND circuit 25a of the circuit 25, the output shown in FIG. 2B is obtained. This output and the output of the exclusive OR circuit 26 (FIG. 2b E) are supplied to the exclusive OR circuit 25b,
Its output is “1” as shown in Figure 2bG.
The output signal (H in FIG. 2B) of the Q output terminal of the flip-flop circuit 25c is supplied to the D input terminal of the flip-flop circuit 17, and the flip-flop circuit 17 outputs the output signal from the Q output terminal (H in FIG. 2B) in synchronization with the clock pulse (A in FIG. 2B). As shown in FIG.
is supplied to the base of transistor 7 through. At this time, transistor 7 operates, so transformer 4
The part from one end of the primary coil 4a to the intermediate tap is used, and its inductance value is L ₁
It is. That is, the maximum output power P ₀₂ at this time is determined by setting the period of the first reference pulse to T _P as well as the second reference pulse, and converting the transformer 4 and the transistor 7.
Letting the efficiency of η ₂ be P ₀₂ = Vi ² · Da ² · T _P · η ₂ /2L ₁ ...(2).

Therefore, when the load on the output terminal 9 is light, the transistor 6 is switched to use the inductance value L ₂ of the entire primary coil 4a of the transformer 4, and when the load on the output terminal 9 is heavy, the primary coil 4a is used.
Inductance value from one end to the middle tap
Since load fluctuations are handled using _L2 , there is no drop in efficiency, and a sufficiently stable DC voltage can be obtained for any load fluctuation.

The relationship between the DC output power and the duty ratio of each reference pulse in Equation (2) for heavy loads and Equation (1) for light loads can be expressed as shown in Figure 3 A and B. can. Here, the minimum value of the duty ratio of the first reference pulse under heavy load is Da ₁ , the power required at that time is Ps ₂ ,
The maximum value of the duty ratio of the second reference pulse at light load is Db ₂ , and the power required at that time is Ps ₁
Then, the most efficient control ability can be obtained by assuming that the efficiencies η ₁ and η ₂ are equal, Ps ₁ = Ps ₂ , i.e. This is the case.

However, in the case of the conventional switching power supply circuit having the above-mentioned configuration, switching may not be performed when the efficiencies η ₁ and η ₂ are not equal, resulting in a disadvantage that the control ability is reduced.

The present invention has been made to eliminate these conventional drawbacks, and provides a switching power supply circuit that can improve control capability without reducing efficiency.

An embodiment of the present invention will be described below, but since its circuit configuration and operation are similar to the conventional switching power supply circuit shown in FIG. 1 and FIG. This will be explained with reference to FIG.

In FIG. 3, Da _{1 is the duty ratio of the first reference pulse when the transistor 7 that is in the on state at heavy loads is switched to the transistor 6, and the duty ratio of the first reference pulse when the transistor 7 is switched to the transistor 6 that is in the on state at the time of a light load is Da 1} ,
The duty ratio of the second reference pulse when switching to _Db2 is set to a constant value, and transistor 7
If the relationship between the output power Ps ₂ when transistor 6 switches to transistor 6 and the output power Ps ₁ when transistor 6 switches to transistor 7 is set so that Ps ₁ > Ps ₂ , switching between transistors 7 and 6 is possible. Instead, hysteresis as shown by the chain line in FIG. 3 occurs. In this case, the pulse width Db ₁ of the pulse width modulator 12 when the load is light is the power when the load is heavy.
Pulse width modulator 12 stabilizes with a pulse width equivalent to Ps ₂ and when the load becomes heavy (when the output current is large)
The pulse width Da ₂ stabilizes at a pulse width equivalent to the power Ps ₁ when the load is light. Therefore, it can be seen that the switching operation of the transistors 7 and 6 is performed in accordance with this hysteresis, so that the control operation is performed smoothly without interruption.

In this case, based on the relationship Ps ₁ >Ps ₂ , the inductance value L ₂ of the entire primary coil 4a of the transformer 4 may be set as follows.

D ² b ₂・η ₁ /L ₂ > D ² b ₂・η ₂ /L ₁ , that is, L ₂ <D ² b ₂・η ₁ /D ² a ₁・η ₂ L ₁ ...(3) Also, the above Hysteresis may be provided by setting the pulse width of the second reference pulse.

As is clear from the above description, according to the switching power supply circuit according to the present invention, the overall inductance value of the primary coil 4a of the transformer 4 is simply set to satisfy equation (3), and the transistors 7 and 6 are By providing hysteresis in the switching operation, both transistors can be switched smoothly, increasing control efficiency without reducing efficiency, and providing stable DC voltage for any load. This is particularly useful when converting into an IC.

In the above embodiment, the case where the primary coil 4a of the transformer 4 has two active terminals has been explained, but the present invention is not limited to this, and the primary coil 4a
Even if there are n terminals in the terminal, when switching the transistors Q ₁ to Q _o connected to these terminals, the inductance values L ₁ to L _o of the coils respectively provided corresponding to each transistor are given by the following formula L( n+1)<D ² b(n+1)・η _(o) /D ² a _(o)・η(
It goes without saying that the same effect as described above can be obtained by setting the value to satisfy n+1)L _o (4).

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an example of a conventional switching power supply circuit, FIGS. 2a to 2c are diagrams for explaining the operation of FIG. 1, and FIG. 3 is a diagram for explaining the basic principle of the present invention. It is a schematic diagram. 3 and 8 are rectifier circuits, 4 is a transformer, 6 and 7 are transistors, 9 is an output terminal, 10 is a voltage detection circuit, 12 is a pulse width modulator, 17 is a flip-flop circuit, 18 and 19 are each an AND circuit, 20a and 20b are reference pulse input terminals, 21, 22 and 24 are NAND circuits, 23
2 is an inverter circuit, and 25 is a comparison circuit.

Claims (1)

[Claims] 1. A first and a second coil connected to a DC input power source through coils each having a predetermined inductance value.
a switching element, a rectifier circuit provided on the output side of the first and second switching elements, a pulse width modulator that generates a switching signal with a pulse width corresponding to the DC output voltage of the rectifier circuit, and a predetermined switching element. a first reference pulse input terminal to which a first reference pulse having a pulse width of is supplied; and a second reference pulse input terminal to which a second reference pulse having a pulse width wider than the first reference pulse is supplied. a reference pulse selection circuit that selects one of the first and second reference pulses depending on which control electrode of the switching element is supplied with the switching signal; a comparison circuit for comparing the reference pulse selected by the pulse selection circuit and the switching signal from the pulse width modulator; 1. A switching power supply circuit comprising: a switching circuit for switching between supplying a signal and providing hysteresis in switching between the first switching element and the second switching element.