JPH0245938A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce gate length by depositing a resist pattern as a mask on a lower gate electrode or forming a gate electrode with its sectional area being in T-shape by plating. CONSTITUTION:A first resist pattern 2 is formed on the main surface of a semiconductor substrate 1 and a recess area 3 is formed by etching. A lower- part gate electrode 4a is formed by depositing an electrode material and eliminating the resist pattern 2. After coating a resist 2' newly, the top part of the lower-part gate electrode 4a is exposed by etching and then coated with resist for patterning to allow a second resist pattern 6 to be formed. By depositing the electrode material and eliminating the resist 2' and the resist pattern 6, a wide upper-part gate electrode 4b is obtained on the lower-part gate electrode 4a. Both gate electrodes are turned into once piece by heat treating and a gate electrode with its sectional area being in T shape is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method for forming a gate electrode that can reduce wiring resistance of a gate electrode of an sFET or the like.

[Conventional technology]

High frequency field effect transistors, especially Schottky barrier field effect transistors using GaAs (GaAs
sMESFET) has already been put into practical use as a microwave transistor that breaks through the characteristic limits of SL bipolar transistors, and has achieved many successes. As a figure of merit in the microwave region, MAG (maximum available
gain) is often used.

Here, fT: Cutoff frequency f: Operating frequency gds Nidrain conductance Ryo: Wiring resistance of gate electrode RI: Channel resistance between source and drain R1: Wiring resistance of source electrode Ll: Common power supply lead inductance Cdg Between Nidrain and gate capacity.

Therefore, in order to achieve higher frequencies and higher gains, it is important to increase fT and reduce parasitic factors such as L+L+Rdl+Cdf by shortening the gate length.

As electrode patterns become finer in order to achieve higher frequencies and higher gains, an increase in electrode wiring resistance, particularly gate electrode wiring resistance R, has become a major factor in deteriorating device performance.

As a method of reducing the wiring resistance R5, a method of increasing the cross-sectional area of the gate electrode is generally adopted. As a conventional example, the mainstream method is to simply increase the thickness of the gate electrode by increasing the resist thickness by making full use of well-known photolithography technology and lift-off technology.

The gate electrode of this type of field effect transistor, etc.
It is formed as shown in Figures (a) to (d). That is,
First, as shown in FIG. 4(a), a resist is applied onto the main surface of the substrate 1, and then gate patterning is performed by photolithography to form a resist pattern 2.

Next, as shown in FIG. 4(b), the gate electrode portion is recessed and etched to form a recess groove 3. Then the fourth
As shown in Figure (C), gate electrode material 5 is deposited on the entire surface. Further, as shown in FIG. 4(d), a gate electrode 4 is formed by removing unnecessary gate electrode material 5 and resist pattern 2 by a lift-off method or the like.

[Problem to be solved by the invention]

In order to improve the performance of high frequency field effect transistors, it is required to shorten the gate length Lg and reduce the gate resistance Rg. In the conventional technology, in order to shorten the gate length Lg, the gate pattern is made thinner and the gate metal 5 is formed by vapor deposition. The rate of increase in area is small, leading to an increase in gate resistance Rg. therefore,
In the conventional example, the gate length L is reduced by suppressing the increase in gate resistance Rg.
There was a problem that g could not be shortened.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress an increase in gate resistance Rg and shorten gate length Lg.

(Means for Solving the Problems) The invention according to claim (1) forms a recess region on a semiconductor substrate using a first resist pattern as a mask, and then forms a lower gate electrode. ,after that,
A gate electrode having a T-shaped cross section is formed on the lower gate electrode by vapor deposition or plating using a second resist pattern as a mask.

In addition, the invention described in claim (2) related to this invention is:
After forming a first resist pattern having an opening corresponding to the gate electrode length on the semiconductor substrate, a covering layer is formed on the entire surface, and then an overhanging second resist pattern is formed on the covering layer.
After forming a resist pattern, and then forming a recess region using the first resist pattern as a mask,
The entire surface is coated with the gate electrode material, and then the first. The second resist pattern and unnecessary gate electrode material are removed to form a gate electrode having a T-shaped cross section.

[Effect]

In the invention described in claim (1) of the invention, a wide upper gate electrode is formed on top of a lower gate electrode whose gate length is shortened by a narrow gate pattern, thereby forming a gate electrode having a T-shaped cross section. By shortening the gate length and increasing the gate cross-sectional area, an increase in gate resistance is suppressed and high frequency characteristics are also improved.

Further, in the invention described in claim (2) of the present invention, since the gate electrode having a T-shaped cross section is formed using an overhanging resist pattern formed on the coating layer, the wiring resistance of the gate electrode is reduced. Ru.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(h) are process sectional views showing an embodiment of the invention as set forth in claim (1) of the present invention. First, the first
As shown in Figure (a), after applying a resist onto the main surface of a semiconductor substrate 1, thin gate patterning is performed by photolithography to form a first resist pattern 2. Next, as shown in FIG. 1(b), the gate electrode portion is recessed and etched to form a recess region 3.

Next, as shown in FIG. 1(C), the gate electrode material 5
Deposit. Next, as shown in FIG. 1(d), the unnecessary gate electrode material 5 and the first resist pattern 2 are removed by a lift-off method or the like to form a lower gate electrode 4a. A new resist 2' is applied to the entire surface so that it is embedded. After that, see Figure 1 (
As shown in e), reactive ion etching (hereinafter referred to as RI)
The resist 2' is thinned by etching (abbreviated as E) or the like, and removed until the top of the lower gate electrode 4a is exposed on the surface of the resist 2'. Furthermore, as shown in FIG. 1(f), a resist is applied to the entire surface and patterned by photolithography to form a second resist pattern 6 having an opening above the gate electrode 4a. Next, in Figure 1 (g
), the exposed surface of the lower gate electrode 4a is lightly etched, and a gate electrode material 7 similar to that on the upper part of the lower gate electrode 4a is deposited. Next, as shown in FIG. 1(h), the resist 2' and the second
The resist pattern 6 and unnecessary gate electrode material 7 are removed to obtain a wide upper gate electrode 4b on the lower gate electrode 4a. Thereafter, heat treatment is performed to integrate the lower gate electrode 4a and the upper gate electrode 4b, forming a gate electrode 4 having a T-shaped cross section.

FIGS. 2(a) to 2(d) are process sectional views showing another embodiment of the invention according to claim (1) of the present invention. In this embodiment, after going through the same steps as in FIGS. 1(a) to 1(e), a plating base metal 8 is formed by vapor deposition or the like, as shown in FIG. 2(a).

Next, as shown in FIG. 2(b), a second resist pattern 6 is formed in the same manner as in FIG. 1(f).

Next, as shown in FIG. 2(C), an upper gate electrode 4c is formed by gold plating. Furthermore, as shown in FIG. 2(d), the second resist pattern 6 is removed, and the excess plating base metal 8 and resist 2' are removed. In this case, after removing the second resist pattern 6 to remove the plating base metal 8, the plating base metal 8 is removed, and then the resist 2' is removed, so the second resist pattern 6 is positive type, and the resist 2' is removed. ′ is better if it is a negative type. By carrying out the above process, a wide upper gate electrode 4c is obtained by plating on the lower gate electrode 4a, and the gate electrode 4 has a T-shaped cross section.
form.

FIGS. 3(a) to 3(h) show an embodiment of the method for manufacturing a semiconductor device according to claim (2) of the present invention, and are sectional views showing main steps of a GaAs MESFET.

First, as shown in FIG. 3(a), for example, AuGe (alloy), Ni and A sample is prepared in which a source electrode 13 and a drain electrode 14 made of three layers of Au are formed at predetermined intervals. After this, as shown in FIG. 3(b), a first resist pattern 15 is formed which has an opening corresponding to the gate length at a desired position between the source electrode 13 and the drain electrode 14, and covers the other parts. form.

Subsequently, as shown in FIG. 3(e), a covering layer 16 is formed over the first resist pattern 15 and over the entire area of the opening by a well-known vapor deposition method or the like. In this case, the covering layer 16
is one that can be easily removed by etching, which will be described later, and that does not alter the quality of the first resist pattern 15 during deposition, and can further prevent the influence of the second resist pattern 17 on the first resist pattern 15. It may be a metal film or an insulating film, if any. Then the third
As shown in Figure (d), an opening having a size equal to or larger than the opening shape of the first resist pattern 15 is located at a position corresponding to the opening of the first resist pattern 150 on the coating layer 16. A second resist pattern 17 having a portion is formed. In this case, the second resist pattern 17 is formed to have an overhanging cross-sectional shape by a well-known solvent immersion method or the like in order to improve the lift-off property during gate lift-off, which will be described later. Thereafter, as shown in FIG. 3(e), using the second resist pattern 17 as a mask, the covering layer 16 exposed on the first resist pattern 15 and in the openings of the first resist pattern 15 is etched. Remove by. Next, as shown in FIG. 3(f), using the first resist pattern 15 as a mask, the n-type GaAs semiconductor layer 12 is etched through the opening so that a predetermined pinch-off voltage or a predetermined drain current is achieved. to form a recess region 18. Next, Figure 3 (
As shown in g), a predetermined gate electrode material 19', for example AJl, is formed to a thickness equal to or greater than the thickness from the surface of the recess region 18 to the surface of the first resist pattern 15. That is, Afl grown from the recessed region 18 and A formed on the first resist pattern 15
It is formed to a thickness that allows λ to be connected. After that, unnecessary first resist pattern 15. By removing the second resist pattern 17 in the covering layer 16 and the gate electrode material 19' on the second resist pattern 17 by lift-off or the like, a cross section T is formed in the recessed region 18 as shown in FIG. 3(h). A gate electrode 19 having a letter shape is obtained.

In this way, the above embodiment has the covering layer 16 in the middle,
By applying a two-layer resist structure of a first resist pattern 15 and a second resist pattern 17 having different opening shapes, the gate electrode 19 is formed to have a T-shaped cross section, and the cross section of the gate electrode 19 is The area is increased, the wiring resistance of the gate electrode 19 can be easily reduced, and the device performance can be improved.

In the above embodiment, the case of a GaAs MESFET was described, but the present invention can be widely applied to field effect transistors made of other materials.

〔Effect of the invention〕

As explained above, the invention according to claim (1) of the present invention forms a wide gate upper electrode on a gate lower electrode with a short gate length, and then processes these upper and lower gate electrodes in an integrated manner. Since a gate electrode with a T-shaped cross section is formed,
As the gate length is shortened, the gate cross-sectional area increases, and gate resistance can be reduced.

In addition, the invention described in claim (2) of the present invention includes a resist pattern having an opening corresponding to the gate electrode in the lower layer and a coating layer, and an opening on the upper layer having an opening equal to or larger than that of the resist pattern in the lower layer. By adopting a two-layer resist structure consisting of a resist pattern with This has the effect of reducing the amount of energy and making it easier to improve the performance of the device.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view of a gate electrode forming method showing one embodiment of the present invention, FIG. 2 is a process cross-sectional view showing another embodiment of the invention, and FIG. FIG. 4 is a process cross-sectional view showing an example of a conventional method for forming a gate electrode. In the figure, 1 is a semiconductor substrate, 2 is a first resist pattern, 3 is a recess groove, 4 is a gate electrode, 5 is a gate electrode material, and 6 is a second resist pattern. 7 is a gate electrode material, 8 is a plating base metal, 11 is a semi-insulating GaAs substrate, 12 is an n-type GaAs semiconductor layer,
13 is a source electrode, 14 is a drain electrode, 15 is a first resist pattern, 16 is a covering layer, 17 is a second resist pattern, 18 is a recess region, and 19 is a gate electrode. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) 1st L Corr-('JF) Ln Figure Figure

Claims (2)

[Claims] (1) A step of forming a first resist pattern on a semiconductor substrate, a step of performing recess etching using this first resist pattern as a mask to form a recessed region, and depositing a gate metal on the front surface and forming a recessed region in the recessed region. forming a lower gate electrode, after removing the first resist pattern and unnecessary gate electrode material, applying a resist so that the lower gate electrode is embedded in the entire surface, and then protruding the lower gate electrode; a step of etching the resist as shown in FIG. 1. A method of manufacturing a semiconductor device, the method comprising the step of removing the resist pattern of No. 2 and unnecessary upper gate electrode material to form a gate electrode having a T-shaped cross section. (2) A step of forming a first resist pattern on the semiconductor substrate, a step of forming a coating layer with a predetermined thickness over the entire surface, and a step of forming a second resist pattern having an overhanging cross-sectional shape at a predetermined position on the coating layer. forming a gate electrode to a predetermined thickness over the entire surface; removing the covering layer exposed by forming the second resist pattern; performing recess etching using the first resist pattern as a mask to form a recess region; the process of depositing the material;
A method for manufacturing a semiconductor device, comprising the step of removing the first and second resist patterns and unnecessary gate electrode material to form a gate electrode having a T-shaped cross section.