JPH0246099Y2 - - Google Patents
Info
- Publication number
- JPH0246099Y2 JPH0246099Y2 JP10853284U JP10853284U JPH0246099Y2 JP H0246099 Y2 JPH0246099 Y2 JP H0246099Y2 JP 10853284 U JP10853284 U JP 10853284U JP 10853284 U JP10853284 U JP 10853284U JP H0246099 Y2 JPH0246099 Y2 JP H0246099Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- delay line
- ground plate
- electromagnetic delay
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 44
- 239000010410 layer Substances 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Waveguides (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Description
【考案の詳細な説明】
〔考案の技術分野〕
本考案は分布定数型の電磁遅延線に係り、特に
GHz帯の高周波信号、または100ps台およびそれ
以下の立ち下がり時間を有する超高速信号に好適
する電磁遅延線の改良に関する。[Detailed description of the invention] [Technical field of the invention] The invention relates to a distributed constant type electromagnetic delay line, and is particularly suitable for high-frequency signals in the GHz band or ultra-high-speed signals with fall times of 100 ps or less. Concerning improvements in electromagnetic delay lines.
この種の電磁遅延線としては、既に本考案者が
超小型、高密度かつ低損失の電磁遅延線を特願昭
59−96145号をもつて開示した。
As for this type of electromagnetic delay line, the present inventor has already proposed an ultra-small, high-density, and low-loss electromagnetic delay line in a patent application.
No. 59-96145.
すなわち、導線路が誘電体層を介してアース板
に形成されるとともに、そのアース板のうち少な
くとも前記導線路に重なるように対向する部分に
導体除去部を形成した電磁遅延線である。 That is, it is an electromagnetic delay line in which a conducting path is formed on a ground plate via a dielectric layer, and a conductor-removed portion is formed at least in a portion of the grounding plate that faces and overlaps with the conducting path.
具体的には、第4図および第5図に示すよう
に、長方形のアース板1に幅a、長さb′の細長い
方形の導体除去部2をピツチdで複数個並行に形
成し、そのアース板1の外周に誘電体層3を形成
するとともに、その誘電体層3の外周に幅ω、厚
さtの導線路4をピツチPで単層ソレノイド状に
スペース巻きした構造を有している。 Specifically, as shown in FIGS. 4 and 5, a plurality of elongated rectangular conductor removal portions 2 having a width a and a length b' are formed in parallel on a rectangular grounding plate 1 at a pitch d. It has a structure in which a dielectric layer 3 is formed on the outer periphery of the grounding plate 1, and a conductive path 4 having a width ω and a thickness t is space-wound around the outer periphery of the dielectric layer 3 in the shape of a single-layer solenoid with a pitch P. There is.
さらに、他の具体例としては、第6図に示すよ
うに、第4図におけるアース板1に円形の導体除
去部5を直交する2方向に僅かの間隔すなわち導
体連結部6をおいて複数個形成したものがある。 Furthermore, as another specific example, as shown in FIG. 6, a plurality of circular conductor removal parts 5 are arranged on the ground plate 1 in FIG. There is something that has been formed.
このような電磁遅延線は、導線路4の幅ωを小
さくすることなく誘電体層3の厚みhを薄くして
も、所望の特性インピーダンスを得ることができ
るばかりか伝播遅延時間を増加させることができ
るので、超小型化および高密度化を図ることが可
能となる。 In such an electromagnetic delay line, even if the thickness h of the dielectric layer 3 is reduced without reducing the width ω of the conducting path 4, it is possible not only to obtain a desired characteristic impedance but also to increase the propagation delay time. This makes it possible to achieve ultra-miniaturization and high density.
しかしながら、このように構成された電磁遅延
線について、さらに検討を加えたところ、構造上
の利点があるものの、生産性の向上および特性の
維持等の観点から改良すべき点のあることが分か
つた。 However, upon further study of the electromagnetic delay line configured in this way, it was found that although it has structural advantages, there are still areas that need improvement from the viewpoint of improving productivity and maintaining characteristics. .
すなわち、第4図および第5図に示す構成の電
磁遅延線を製造する場合、便宜上アース板1に予
め細長い導体除去部2をエツチング等で形成し、
その後にアース板1を誘電体層3に熱圧着等で接
着する手法が採用されている。 That is, when manufacturing an electromagnetic delay line having the configuration shown in FIGS. 4 and 5, for convenience, an elongated conductor removal portion 2 is formed in advance on the ground plate 1 by etching or the like.
Thereafter, a method is adopted in which the ground plate 1 is bonded to the dielectric layer 3 by thermocompression bonding or the like.
しかし、導体除去部2は、第4図からも分かる
ように、幅a、長さb′で電磁遅延線の長手方向一
杯に形成されているから、熱圧着時の圧力によつ
て導体除去部2の幅aの寸法が目的の値よりも大
きくなつたり小さくなつて変形し易く、特性の安
定化を図るために熱圧着作業を慎重にする必要が
あり、生産性が向上しない。 However, as can be seen from FIG. 4, the conductor removed portion 2 is formed to have a width a and a length b', extending completely in the longitudinal direction of the electromagnetic delay line. The dimension of the width a of 2 becomes larger or smaller than the intended value and easily deforms, and the thermocompression bonding operation must be done carefully in order to stabilize the characteristics, which does not improve productivity.
この点、第6図に示す構成の電磁遅延線にあつ
ては、アース板1が熱圧着時の圧力によつて変形
することはないが、導体除去部5と導体連結部6
が交互に電磁遅延線の軸と直交する2方向へ並ん
で配置されているので、導線路4のピツチPや幅
ωとアース板1の諸寸法の関係によつては、導線
路4に対向するアース板1において導体除去部5
の多い部分と導体連結部6の多い部分とが生じ
る。 In this regard, in the case of the electromagnetic delay line having the configuration shown in FIG.
are arranged alternately in two directions perpendicular to the axis of the electromagnetic delay line. Conductor removal part 5 on earth plate 1
There are parts where there are many conductor connecting parts 6 and parts where there are many conductor connecting parts 6.
そのため、導体除去部5が多い部分では導線路
4の特性インピーダンスが高くなり、導体連結部
6が多い部分では導線路4の特性インピーダンス
が低くなつて導線路4の特性インピーダンスにば
らつきが生じ、やはり特性の安定化を図り難い場
合がある。 Therefore, the characteristic impedance of the conducting line 4 becomes high in the part where there are many conductor removed parts 5, and the characteristic impedance of the conducting line 4 becomes low in the part where there are many conductor connecting parts 6, resulting in variations in the characteristic impedance of the conducting line 4. It may be difficult to stabilize the characteristics.
本考案はこのような状況の下になされたもの
で、生産性が良好で特性の維持が可能であるう
え、超小型、高密度かつ低損失の超高速電磁遅延
線の提供を目的とする。
The present invention was developed under these circumstances, and aims to provide an ultra-high-speed electromagnetic delay line that has good productivity, maintains its characteristics, is ultra-small, has high density, and has low loss.
この目的を達成するために本考案は、導線路が
誘電体層を介してアース板に形成されてなる電磁
遅延線において、前記アース板に導体除去部が導
体連結部を介して上下左右方向に複数形成される
とともに、前記上下もしくは左右方向に連なる導
体除去部が前記上下もしくは左右方向に対して斜
めに配置したものである。
In order to achieve this object, the present invention provides an electromagnetic delay line in which a conductor line is formed on a ground plate through a dielectric layer, in which a conductor removal part is connected to the ground plate in vertical and horizontal directions via a conductor connection part. A plurality of conductor removal portions are formed, and the conductor removal portions that are continuous in the vertical or horizontal direction are arranged diagonally with respect to the vertical or horizontal direction.
このような本考案の構成によれば、超小型化、
高密度化、損失の低下等の高い性能を維持しつ
つ、生産性の向上を図ることができる。 According to the configuration of the present invention, ultra-miniaturization,
It is possible to improve productivity while maintaining high performance such as high density and reduced loss.
以下、本考案の詳細を説明する。 The details of the present invention will be explained below.
第1図および第2図は本考案の電磁遅延線に係
る一実施例を示す正面図および側面図である。 1 and 2 are a front view and a side view showing an embodiment of the electromagnetic delay line of the present invention.
両図において、長方形の薄いアース板7の外周
には誘電体層8が形成され、アース板7の長手方
向両端部が誘電体層8から突出している。 In both figures, a dielectric layer 8 is formed on the outer periphery of a rectangular thin earth plate 7, and both longitudinal ends of the earth plate 7 protrude from the dielectric layer 8.
誘電体層8の外周には、幅ω厚みtの導線路9
がピツチPで単層ソレノイド状にスペース巻きさ
れ、分布定数型の電磁遅延線が構成されている。 On the outer periphery of the dielectric layer 8, there is a conductive line 9 having a width ω and a thickness t.
is space-wound in the shape of a single-layer solenoid at pitch P, forming a distributed constant type electromagnetic delay line.
第2図中符号hはアース板7の片面側における
誘電体層8の厚み、符号Tはアース板7を挟んで
対向する導線路9中心間の距離である。 In FIG. 2, the symbol h is the thickness of the dielectric layer 8 on one side of the ground plate 7, and the symbol T is the distance between the centers of the conductive lines 9 facing each other with the ground plate 7 in between.
そして、上記アース板7にはその長手方向(第
1図中左右方向)に沿つて幅a、長さbの長方形
の導体除去部10が間隔eすなわちアース板7の
一部たる導体連結部11をおいて直列に複数個形
成され、これら導体除去部10の列が複数段アー
ス板7の幅方向(第1図中上下方向)に形成され
ている。 The ground plate 7 is provided with rectangular conductor removal parts 10 having a width a and a length b along its longitudinal direction (left-right direction in FIG. A plurality of conductor removed portions 10 are formed in series with each other, and rows of these conductor removal portions 10 are formed in the width direction (vertical direction in FIG. 1) of the multi-stage earth plate 7.
しかも、各列の導体除去部10は、アース板7
の幅方向(上下方向)に対して順次斜めにずれて
形成され、アース板7の幅方向に対して角度θで
斜めに配置されている。 Moreover, the conductor removal portions 10 in each row are connected to the ground plate 7.
They are formed to be sequentially shifted diagonally with respect to the width direction (vertical direction) of the earth plate 7, and are arranged diagonally at an angle θ with respect to the width direction of the ground plate 7.
なお、導線路9のピツチPとアース板7を挟ん
で対向する導線路9の中心間隔Tは、実用的なパ
ルス応答波形の得られる範囲とし、0<T/P<
1の範囲で選定されるのが好ましい。 The pitch P of the conductive line 9 and the center distance T of the conductive line 9 facing each other with the ground plate 7 in between are within a range that allows a practical pulse response waveform to be obtained, and 0<T/P<
It is preferable to select within the range of 1.
このように構成された電磁遅延線は、導体除去
部10が短く形成されて第4図の如くアース板7
の長手方向一杯に形成されていないうえ斜めに少
しづつずれて配置されているから、たとえ導体除
去部10を形成したアース板7を誘電体層8に熱
圧着する場合にも、細長い導体除去部10が変形
しにくくなつてアース板7の扱いが簡単となり、
製造能率が向上する。 In the electromagnetic delay line configured in this way, the conductor removed portion 10 is formed short and the ground plate 7 is formed as shown in FIG.
Because they are not formed completely in the longitudinal direction and are arranged diagonally and slightly shifted, even when the grounding plate 7 on which the conductor removed portion 10 is formed is thermocompression bonded to the dielectric layer 8, the elongated conductor removed portion 10 is less likely to deform, and the ground plate 7 is easier to handle.
Manufacturing efficiency improves.
しかも、上述したように、導線路9と重なるア
ース板7部分に導体除去部10が部分的に形成さ
れるので、導線路9のインダクタンスが増加し、
その増加分だけ静電容量も大きくして特性インピ
ーダンスを同様に保つことが必要となるが、静電
容量を形成する導体面積が減少しているので、誘
電体層8の厚みhを十分に薄くすることで必要な
静電容量を得ることができる。 Moreover, as described above, since the conductor removal portion 10 is partially formed in the portion of the ground plate 7 that overlaps with the conductor line 9, the inductance of the conductor line 9 increases,
It is necessary to increase the capacitance by that increase in order to maintain the same characteristic impedance, but since the conductor area that forms the capacitance is decreasing, the thickness h of the dielectric layer 8 must be made sufficiently thin. By doing so, the necessary capacitance can be obtained.
すなわち、誘電体層8の厚みhを十分薄くでき
るので、導線路9のピツチP及び間隔Tを小さく
することが可能となるので、超小型化および高密
度化が可能となる。 That is, since the thickness h of the dielectric layer 8 can be made sufficiently thin, the pitch P and the interval T of the conductive lines 9 can be made small, so that ultra-miniaturization and high density can be achieved.
さらに、導線路9の幅ωを同じに保つたまま単
位長さ当たりの伝播遅延時間が大きくなるので、
超小型化を図りながら単位遅延時間当たりの損失
が逆に低下するので、一層高性能とすることがで
きる。 Furthermore, since the propagation delay time per unit length increases while keeping the width ω of the conducting path 9 the same,
Since the loss per unit delay time is conversely reduced while achieving ultra-miniaturization, even higher performance can be achieved.
アース電極7に形成する導体除去部の形状は、
上述した第1図に示す長方形に限らない。例え
ば、第3図に示すように、円形の導体除去部12
をアース板7の長手方向および幅方向に導体連結
部13を介して複数形成するとともに、幅方向に
連なる円形の導体除去部12を幅方向に対して角
度θで斜めにずらして配置してもよい。なお、図
示は省略したが誘電体層8および導線路9の構成
は同じである。 The shape of the conductor removed portion formed in the ground electrode 7 is as follows:
The shape is not limited to the rectangle shown in FIG. 1 described above. For example, as shown in FIG.
A plurality of conductor connecting parts 13 are formed in the longitudinal direction and the width direction of the ground plate 7, and the circular conductor removal parts 12 connected in the width direction are arranged diagonally at an angle θ with respect to the width direction. good. Although not shown in the drawings, the configurations of the dielectric layer 8 and the conductive line 9 are the same.
このように構成した電磁遅延線は、導線路9に
対するアース板7は導体除去部12と導体連結部
13とが分散して配置されるので、導線路9の特
性インピーダンスのばらつきも分散され、特性へ
の影響が抑えられて特性が安定する。 In the electromagnetic delay line configured in this way, since the conductor removal section 12 and the conductor connection section 13 are arranged in a distributed manner on the ground plate 7 for the conductor line 9, variations in the characteristic impedance of the conductor line 9 are also dispersed, and the characteristic The characteristics are stabilized by suppressing the influence on
さらに、導体除去部の形状は、これら以外にも
三角形や六角形等でもよく、要は、アース板7に
あつて上下もしくは左右方向の直交する2方向に
導体除去部を形成するとともに、その上下もしく
は左右方向に連なる導体除去部をその上下もしく
は左右方向に対して斜めに配置すれば、本考案の
目的を達成できる。 Furthermore, the shape of the conductor removed portion may be triangular, hexagonal, etc. other than these, and the point is that the conductor removed portion is formed in two orthogonal directions of the top and bottom or left and right directions of the ground plate 7, and Alternatively, the object of the present invention can be achieved by arranging the conductor removal portions extending in the left-right direction obliquely with respect to the upper and lower directions or the left-right direction.
また、本考案の電磁遅延線にあつては、導線路
9のピツチPと間隔Tの関係がT/P=0の場
合、すなわちマイクロストリツプ導線を平面的に
矩形状や三角形状等に折り曲げて形成する場合で
あつても実施可能であり、さらに渦巻き状や単に
直線的に形成することも可能である。 In addition, in the case of the electromagnetic delay line of the present invention, when the relationship between the pitch P and the interval T of the conductor line 9 is T/P=0, that is, the microstrip conductor is formed into a rectangular or triangular shape in a plane. It is possible to form it by bending it, and it is also possible to form it in a spiral shape or simply in a straight line.
以上説明したように本考案の電磁遅延線は、小
型化、高密度化および低損失化等高い性能を維持
しつつ、製造能率の向上を図ることができる。 As explained above, the electromagnetic delay line of the present invention can improve manufacturing efficiency while maintaining high performance such as miniaturization, high density, and low loss.
第1図および第2図は本考案に係る電磁遅延線
の一実施例を示す正面図および側面図、第3図は
第1図に示すアース板の他の例を示す部分正面
図、第4図および第5図は本考案の電磁遅延線の
参考となる電磁遅延線を示す正面図および側面
図、第6図は第4図の電磁遅延線におけるアース
板の他の例を示す部分正面図である。
1,7……アース板、2,5,10,12……
導体除去部、3,8……誘電体層、4,9……導
線路、6,11,13……導体連結部。
1 and 2 are front and side views showing one embodiment of the electromagnetic delay line according to the present invention, FIG. 3 is a partial front view showing another example of the ground plate shown in FIG. 1, and FIG. 5 and 5 are front and side views showing an electromagnetic delay line as a reference for the electromagnetic delay line of the present invention, and FIG. 6 is a partial front view showing another example of the ground plate in the electromagnetic delay line of FIG. 4. It is. 1, 7...Earth plate, 2, 5, 10, 12...
Conductor removed portion, 3, 8...dielectric layer, 4, 9...conductor path, 6, 11, 13...conductor connection portion.
Claims (1)
てなる電磁遅延線において、前記アース板に導体
除去部が導体連結部を介して上下左右方向に複数
形成されるとともに、前記上下もしくは左右方向
に連なる導体除去部が前記上下もしくは左右方向
に対して斜めに配置されてなることを特徴とする
電磁遅延線。 In an electromagnetic delay line in which a conducting path is formed on a ground plate via a dielectric layer, a plurality of conductor removal parts are formed on the ground plate in the vertical and horizontal directions via conductor connecting parts, and the conductor removal parts are formed in the vertical and horizontal directions. An electromagnetic delay line characterized in that conductor removal portions connected to are arranged diagonally with respect to the vertical or horizontal direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10853284U JPS6123716U (en) | 1984-07-18 | 1984-07-18 | electromagnetic delay line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10853284U JPS6123716U (en) | 1984-07-18 | 1984-07-18 | electromagnetic delay line |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6123716U JPS6123716U (en) | 1986-02-12 |
| JPH0246099Y2 true JPH0246099Y2 (en) | 1990-12-05 |
Family
ID=30667714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10853284U Granted JPS6123716U (en) | 1984-07-18 | 1984-07-18 | electromagnetic delay line |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6123716U (en) |
-
1984
- 1984-07-18 JP JP10853284U patent/JPS6123716U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6123716U (en) | 1986-02-12 |
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