JPH0246591A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To classify whether a cause is due to the erroneous storing of a memory cell itself or the delay of the communication time of data when the trouble of reading occurs at a device by providing a fuse to switch to a means to hold a reading action condition only when an address transition does not occurs after an address transition. CONSTITUTION:When the fuse F provided in a program circuit 12 is not cut, a reading completion clock is generated, and when the fuse F is cut, the generation of a reading completion clock is prohibited. Namely, when the fuse F is cut, an output edge A of a flip flop circuit is fixed to a high level, the output of a NOR circuit 14 is always fixed to a Low level without depending on the output signal of an address transition detecting circuit 2 and both input signal and output signal of a reading completion clock generating circuit 4 become high levels. Thus, when the trouble of the reading occurs, it can be easily judged whether the cause is due to the erroneous storing of a memory cell itself or the delay of the communication time of reading data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to an internally synchronous static RAM type semiconductor memory device.

[Conventional technology]

Conventionally, this type of semiconductor memory device, in particular, has an address transition detection circuit, generates a one-shot pulse when the input address signal changes, and uses the one-shot pulse as an internal synchronization signal to determine the timing of start and end of reading. The internal operation control circuit of such an internally synchronized static RAM is normally constructed as shown in FIG.

The input address signal is input to an address buffer 1, and the output of the address buffer 1 is input to an address transition detection circuit 2. When the address signal transitions, a one-shot pulse is generated as an address transition detection signal.

The one-shot pulse is input to the read start clock generation circuit 3 and the read end clock generation circuit 4, and the respective outputs are ANDed to generate a sense amplifier activation signal, a precharge signal, a word Internal control signal (φi) that generates line activation signals, etc.
Connected to the generator circuit.

FIG. 5 is a timing chart after address transition during reading. After the address transition, the address transition detection circuit 2 generates a one-shot pulse, the read start clock generation circuit 3 outputs a pulse with the opposite phase to the one-shot pulse, and the read end clock generation circuit 4 outputs a one-shot pulse. A waveform with the pulse width of the shot pulse expanded is output. In the internal control signal generation circuit 5, the timing of rising from a low level to a high level is determined by the rising edge of the read start clock;
A signal whose timing of falling to the OW level is determined by the rise of white after completion of reading is input, and a control signal φi having the same phase as this input signal is generated.

During the period when the control signal φi is Low after address change, the digit line load circuit 6 and the data bus load circuit 7 are driven.
While the digit lines and data bus lines are precharged, the word line drive circuit 8 is reset and all word lines are lowered. Further, at this time, the sense amplifier 9 is also reset, and the read data for all cycles held in the data latch circuit 10 is outputted to the outside via the output buffer circuit 11.

When the control signal φi changes from Low to High, precharging of the digit line and data bus is completed, the word line corresponding to the output signal of the X decoder rises, and information is transmitted from the memory cell to the digit line.

Furthermore, information on the only digit line selected by the output signal of the Y decoder is transmitted to the data bus line via the row selection transistor. Control signal φi from Low to High
In response to the change, the sense amplifier 9 is also activated, outputs an amplification signal, and transfers the normal read data to the data latch circuit 1.
At the same time as writing to 0, read data is output to the output terminal via the output buffer circuit 11.

When writing to the data latch circuit 10 is completed, the control signal φi changes from High to Low again, the digit line and data bus line enter the precharge state, all the word lines fall, and the sense amplifier is also reset. .

[Problem to be solved by the invention]

In the above-mentioned conventional semiconductor memory device, during a read operation of an internally synchronous static RAM, if the output from the output buffer circuit is not normal read data but erroneous read data after the address transition, some cause may occur. This problem occurred because normal read data could not be transmitted to the data latch circuit during the period when the internal operation control signal φi was high, that is, during the period when the internal read operation was in progress. The disadvantage is that it is difficult to distinguish between a defect and whether incorrect information has been stored in the memory cell itself.

An object of the present invention is to easily switch from a method in which the read operation period after an address change is limited to a certain fixed period by an internal synchronization signal to a method in which the read operation state is maintained as long as an address change does not occur. It is possible and
If a reading problem occurs in the device, by performing the above-mentioned switching, it is possible to distinguish whether the cause of the problem is due to erroneous storage in the memory cell itself or a delay in data transmission time. The goal is to provide equipment.

[Means to solve the problem]

The semiconductor memory device of the present invention is an internally synchronized static RAM that performs an internal operation using an address transition detection signal generated by an address transition detection circuit as an internal synchronization signal after an address transition. The device includes a flip-flop having a fuse for switching from a device that is limited to a certain period of time by an internal synchronization signal to a device that maintains a read operation state unless an address transition occurs.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an internal operation control circuit according to a first embodiment of the present invention. The difference between this embodiment and the conventional example is that, as a method of inhibiting the generation of the read end clock, a program circuit 1 including a fuse F is provided on the same chip as the semiconductor memory device.
2 is added, and when the fuse F is not cut, the read end clock is generated as in the conventional case, and when the fuse F is cut, the read end clock is prohibited from being generated.

The program circuit 12 has a fuse F added and an Nch
It is composed of an inverter using a MOS FETQ as a driver, a flip-flop circuit composed of a first CMOS inverter 13, a NOR circuit 14, and a second CMOS inverter 15.

The operation of this circuit will be explained below.

When the fuse F is not cut, the output terminal A of the flip-flop circuit is fixed at a low level. Therefore NOR
The output of the circuit 14 always generates a signal with a phase opposite to that of the output of the address transition detection circuit 2.

The output of the CMOS inverter 15 cascade-connected to the R circuit 14 generates a signal in phase with the output of the address transition detection circuit 2 as an input signal to the read end clock generation circuit 4 . Therefore, when the fuse F of the program circuit 12 is not blown, the internal operation similar to the conventional one is performed.

Next, the case when the fuse F is disconnected will be explained. FIG. 2 shows a timing chart at this time.

When fuse F is disconnected, output terminal A of the flip-flop circuit
is fixed at High level, and the output of the NOR circuit 14 is always Low regardless of the output signal of the address transition detection circuit 2.
It is fixed at the OW level, and both the input signal and the output signal of the read end clock generation circuit 4 become High level.

As a result, the control signal φi, which is the output of the internal operation control signal generation circuit 5, is determined only by the read start clock.
This signal is in phase with the read start clock.

In this case, the operation of the semiconductor memory device of the present invention is as follows.
After the address changes, precharging is performed while the control signal φi determined by the read start clock is Low, and then when the control signal φi changes from Low to High, the selected word line rises and the sense amplifier is activated. The read operation starts.

Since the read end clock is disabled, the read operation state changes next and the control signal φi
This continues until becomes Low. Therefore, even if there is a delay in data transmission for some reason, correct information can ultimately be transmitted to the output terminal.

FIGS. 3(a) and 3(b) are circuit diagrams of a second embodiment of the present invention.

The difference from the first embodiment is that the input terminal of the NOR circuit 14, into which the output of the program circuit 12 is input, is made of aluminum wiring in binary instead of the output of the program circuit, and is connected to V c c + G N D. When connected to cc, the operation is the same as in the conventional example, and when connected to cc, the operation is the same as when the fuse is disconnected.

〔Effect of the invention〕

As explained above, the present invention switches from a method in which the read operation period is limited to a certain fixed period by an internal synchronization signal after an address change to a method in which the read operation state is maintained as long as an address change does not occur. Therefore, if a read failure occurs in a semiconductor memory device, it is difficult to determine whether the cause of the failure is due to incorrect memory in the memory cell itself.
This has the effect of making it possible to determine whether the problem is due to a delay in the transmission time of read data.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a timing chart when the fuse in FIG. 1 is disconnected, and FIGS. 2 is a circuit diagram showing an example of the conventional example; FIG. 4 is a block diagram showing an example of a conventional example;
The figure is a timing chart showing the operation of FIG. 4. DESCRIPTION OF SYMBOLS 1... Address buffer, 2... Address transition detection circuit, 3... Read start clock generation circuit, 4...
- Read end clock generation circuit, 5... Internal operation control signal generation circuit, 12... Program circuit, 13...
・Inverter, 14...NOR circuit, 15...Inverter, F...Fuse, Q...O8FET between N channels,
φi...Control signal.

Claims (1)

[Claims] In an internally synchronized static RAM that performs internal operations using an address transition detection signal generated by an address transition detection circuit as an internal synchronization signal after an address transition,
Includes a flip-flop having a fuse for switching from a means in which the read operation time is limited to a certain fixed period by an internal synchronization signal to a means in which the read operation state is maintained as long as an address transition does not occur after an address transition. A semiconductor memory device characterized by: