JPH0447600A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To turn the semiconductor memory device whose ATD circuit does not operate normally by the fluctuation, etc., of process to acceptable product by controlling the usage propriety of an address transition detection (ATD) circuit. CONSTITUTION:Since an output 18 of a storage element 17 for usage propriety of ATD circuits 14 and 15 outputs an 'L' level when nothing is done, a ROM is operated by using the ATD circuit. On the other hand, the normal operation is not performed because the ATD circuits 14 and 15 are used, and a fuse 19 is cut when stopping the usage of the ATD circuits 14 and 15. Then, since the output 18 of the storage element 17 outputs the 'H' level, the ATD output outputs the 'H' pulse at all times without generating the 'L' pulse even when all the input of an NOR circuit 15 becomes the 'L' level and an 'L' pulse in generated in the output of the circuit 14 by transferring the address, and a sense amplifier comes to be unaffected by the ATD circuit. Thus, the ROM is normally operated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor memory device.

[Conventional technology]

Figure 2 shows a conventional ROM (read-only memory): R@ac
FIG. 2 is a block diagram showing the circuit configuration of L 0nly M@mory ). In the figure % (1) e (2)
is the address input x 7a and the X direction address input terminal j (
Mu OS4! ! )! Direction address input terminal @ (no-B
The address input buffer (1) receives the address input signal from !n). The address input buffer (2) receives the direction address and receives the address input signal! Receive direction address. (3) is X
It is a decoder and is connected to the address buffer (2) and its output! It is sent to the gate circuit (8). (4)
is connected to the address input buffer (1) by an X decoder. The output of the X decoder (4) is the memory transistor (
5) word line (6) K is connected. The source of the memory transistor (5) is grounded to GND, and the drain is connected to the pit line (9)! It is connected to the gate circuit (8). ■ is address transition detection (Mujar/mouth Tya)
0 sense amplifier @ F which generates a pulse and sends it to the sense amplifier @ every time the address changes.
In response to the output node αG from the ir gate circuit (8),
It is used to judge stored information, and the output of the sense amplifier ω
is sent to the output buffer (to).

Memory information (51) of a predetermined memory transistor (5) obtained through the output buffer 3/Ii sense amplifier υ
A power is applied to the output terminal (Do ~ DK >) from the output terminal (Do ~ DK >). Also, the specific circuit e of the Mu TD circuit is shown in Figure 3 with the output of 0 and the output of Bn from 0 and b!lt. ``1 creates each circuit, its output &tll&Q &td
b21t is input to the Mo1 circuit (2), and at its output side t, M! making p. The gate input signal α of the exposed transistor of the MoIL circuit is set so that the %H# level is always output.

Next, the operation will be explained. First, the address input signal input to the X-direction address input terminal ω (muO~mum) is! It is a direction address, is amplified and waveform-shaped by the address input cover 27a (1), and is transmitted to the X decoder (4)K @Similarly! Direction address human power bottle ■ (BOM-/!l
! The address input signal input to l ) is! This is a direction address, which is amplified and waveform-shaped by the address input (2) and then reaches the X decoder (3). A predetermined word line (6) is selected by the X decoder (4) 0! Decoder (3) selects word line (6) almost at the same time as X decoder (4)! Gate circuit (8
) to select a predetermined bit line (9). Only this selected bit line (9)! Gate circuit (8
) and connect it to the sense amplifier (2).

The word line (6) and bit line (9) selected by the X decoder (4) and the
5) is selected, and the memory information of the memory transistor (5) is displayed! It is read out through the gate circuit (8), sense amplifier (2), and output buffer 7.

By the way, for the address input signal input from the X-direction address input terminal ω (mu0 to mm) and the r-direction address input terminal @ (Bo-B21>), 17-do data represented by each bit of dDo to Dy is Signals are read out at the same time, and normally one word is made up of several bits, but here only the circuit related to one bit in the word is shown, and the memory transistor (
5), bit line (9).

The sense amplifiers (12, at cover 7A0) are provided in parallel for the number of bits in one word, but these are omitted.The selected memory transistor (5) has the memory information written in it %1# If , bit line (9)
When the memory information is 10#, it is kept non-conductive. The information whether the bit line (9) is grounded or not is detected by the sense amplifier (2), and depending on the detection, %1 or % is detected.

The signal 'I' is input to the output X7Aro, amplified and waveform-shaped, and then output as a signal Do. The signal DO indicates one bit of the one word signal (Do to Dy) determined by the X direction address signal (MU0 to MUSI) and the X direction address signal (BowBn).
As explained earlier, the other bits are outputted through other circuits not shown.Here, the TD circuit (■) is the circuit shown in Figure 3,
If at least one of the X-direction address input signals (Mu0 to Mn) and the Y-direction address input signals ()o to Bm) is switched from the town level μ to the 5L medium level or from the %L# level to the 1H# level. When the signal changes, the 'L# bus signal is output as the MUTD. This signal is input to the sense amplifier UK. That is, when the input signal TD pulse is applied, the input node Ql of the sense amplifier υ and the sense amplifier's output signal are respectively output to the memory information ゜1#10'. t MloTJy N
1611, the intermediate potential M1om of IJ14L, respectively.
+M1oxr /2 # Precharged to M1ha + N1b'L/l. In this situation, sense amplifier (
When the memory transistor (5) is selected according to the normal address input signal and the memory f'l information starts to be read, the memory information is read from 0# to 41 or from 1#. Even if there is a cut to %0#, node a
Since O is precharged to N10t+NjOL72 ic, node α according to the memory information
As soon as G changes, it is recognized and the sense amplifier (L2
starts working. Furthermore, since the output of the sense amplifier (2) is precharged in advance, even the slightest change in the sense amplifier υ is immediately recognized and starts operating. In the end, the output ω of the node αa1 sense amplifier is also Mu! Using the p signal, the change that K causes is h
1←% Not L umbrella, NfoL+N1011 to - evening or N1oz+N1o! I,/! ! It was used because it could recognize 'H#/%L?' in 4h''L' from /2 to 4h''L', which is half the normal speed, and could speed up the access time.

[Problem to be solved by the invention]

Since the conventional 101 circuit is configured as above,
As shown in FIG. 3, the mu τp circuit determines the pulse width by a delay circuit using capacitance. Therefore, there is a problem that the TD does not operate normally due to process fluctuations.

The present invention has been made to solve the above-mentioned problems, and aims to provide a device that can externally control whether or not to use the MuTD circuit.

[Means to solve wiM]

The semiconductor memory device according to the present invention is one in which the use of the MuTD circuit can be controlled from the outside. The D circuit stores its use in an internally clouded memory element, and allows information to be written to the memory element from the outside.

〔Example〕

An embodiment of a semiconductor memory device according to the present invention will be described below with reference to the drawings. Figure 1 shows the MuTD used in the nov circuit.
It is a circuit diagram of a circuit. In the figure, U and aS are the same as those shown in the conventional example of FIG. 3, so their explanation will be omitted. A memory element that stores whether or not the wholesaler uses the TD circuit 0;
(2) is the output of the storage element α, and ■ is the fuse.

Next, the operation will be explained. If there is no normal side, it will be TD.
The output (to) of the memory element node indicating whether or not the circuit ■ can be used is 4 L.
Since the I level is output, the operation of the MTD generating circuit is exactly the same as that of the conventional circuit, and the circuit operates using the J and TD circuits U. On the other hand, when the Mu TD circuit 0 is not used and the Mu TD circuit 0 is no longer used, the fuse is cut off.

Then, the output side of the storage element side of the circuit 0 availability outputs h2 rep ~, so all the inputs of the NOR circuit @ are S L ? level and the address transitions to circuit U.
Even if 4 p # pulses occur at the output of
L'pass)v is not generated and H'vbe)v is always output. In this way, the sense amplifier (2) is no longer influenced by the ATI) circuit (2).

In the above embodiment, A? A fuse (to) was used for memory element 0 for the D circuit 0 availability, but the AT11 circuit■Circuit availability element section contains UPROM (Un@rasab
le programmable! fa60-n1y
Memory) may also be used.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to externally control whether or not the MTD circuit can be used, so that the MTD circuit can be used even in cases where the t)hrD circuit does not operate normally due to process variations, etc. This has the effect of making it possible to operate normally without causing damage, and making it possible to make a product that was previously considered defective to be a good product.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a ROM TD circuit according to an embodiment of the semiconductor memory device according to the present invention, FIG. 2 is a block diagram showing a conventional IO- circuit configuration, and FIG. 3 is used in the ROM shown in FIG. FIG. In the figure, 0 is a circuit, 0 is a NOR circuit or a memory element, (to) is an output, and (2) is a fuse. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] At least an address input buffer circuit, a decoder circuit,
In a semiconductor integrated circuit device having peripheral circuits such as a sense amplifier circuit, an output buffer circuit, and an address transition detection circuit, and a group of memory transistors arranged in a matrix,
1. A semiconductor memory device comprising a memory element for storing whether or not an address transition detection circuit is to be used, the use of the address transition detection circuit being made possible by writing into the memory element from the outside.