JPH0246761A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the operation speed of a bipolar transistor, and unnecessitate the contact of a collector in a field region by burying a high melting point metal film under the bipolar transistor in a single crystal silicon film, and burying a conductor turning to the gate electrode of a vertical type MOS transistor and a conductor in contact with the high melting point metal film, in a groove of trench isolation. CONSTITUTION:In a trench groove 12 in which polycrystalline silicon 17 is buried, a part of a high melting point metal film 6 buried under the lower part of a field region is exposed, and comes into contact with the polycrystalline silicon 17 in the trench groove 12. In the field region, a P-type base region 18 and an N-type emitter region 20 are formed, and a bipolar transistor is constituted. The polycrystalline silicon 17 in the trench groove 12 is connected with a collector region 8. An N-channel MOS transistor is constituted in a single crystal silicon film 8 in a manner as follows; a region 24 turns to a drain, a region 22 turns to channel region, the single crystal silicon film 8 turns to a source, a silicon oxide film 14 turns to a gate oxide film, and a polycrystalline silicon 16 turns to a gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device including a MOS transistor as a load of a bipolar transistor.

(Prior Art) In semiconductor integrated circuit devices having bipolar transistors, the area of the transistors is reduced by using dielectric isolation as element isolation. If the resistance of the impurity diffusion layer is used as a load, the area becomes large and the degree of integration cannot be increased. N of
A semiconductor integrated circuit device including a channel MoS transistor has been proposed (see Japanese Patent Laid-Open No. 122165/1983).

(Problems to be Solved by the Invention) In the semiconductor integrated circuit device of the reference, the bipolar transistor has a structure having a highly doped buried layer epitaxially grown below the collector region. Therefore, the operating speed of the bipolar transistor is the same as that of the conventional transistor, and it is necessary to provide a contact in the field region in order to extract current from the collector.

The present invention uses a vertical MO as a load for a bipolar transistor.
In a semiconductor integrated circuit device equipped with an S transistor,
It is an object of the present invention to provide a semiconductor integrated circuit device that can increase the operating speed of a bipolar transistor, eliminate the need for a collector contact in a field region, and further increase the degree of integration.

(Means for Solving the Problems) In the present invention, a single crystal silicon film is formed on an insulator,
A bipolar transistor and a vertical MOS transistor are formed sharing a part of the field region in the field region separated by the trench isolation method of the single crystal silicon film. A high melting point metal film or a high melting point metal alloy film is buried in the lower part, and the vertical MOS is buried in the trench isolation groove.
A conductor serving as a gate electrode of the transistor and a conductor contacting the high melting point metal film or the high melting point metal alloy film are embedded.

(Function) The collector current of the bipolar transistor is taken out from the high melting point metal film or the high melting point metal alloy film through the conductor in the trench groove. A contact region for taking out the collector current exists on the trench groove for element isolation, and no region for the collector contact is required in the field region.

The resistance value of the high melting point metal film or the high melting point metal alloy film is lower than the resistance value of the conventional diffusion layer, which is a buried layer, so that the operating speed of the bipolar transistor is increased.

(Example) FIG. 1 depicts one embodiment.

2 is a silicon substrate, on the surface of which a silicon oxide film (SiO2) 4 is formed by thermal oxidation. W on the silicon oxide film 4.

A film of a high melting point metal such as Mo or Ti (or a film of a high melting point metal alloy such as their silicide) 6 is formed and patterned. An N-type wheel crystal silicon substrate is formed on the silicon oxide film 4 and the high melting point metal film 6. Field regions separated by a trench isolation method are formed in the single crystal silicon film 8.

The side walls of the isolation trenches 10 and 12 are insulated with a silicon oxide film 14 having a thickness of approximately 5050 mm.
Polycrystalline silicon 16 and 17 are insulated from each other within 12.
is embedded. Impurities are introduced into the polycrystalline silicon 16 and 17 to lower the resistance. polycrystalline silicon 1
A part of the refractory metal film 6 buried in the lower part of the field region is exposed in the trench groove 12 in which the polycrystalline silicon 7 is buried, and is in contact with the polycrystalline silicon 17 within the trench groove 12 .

A P-type base region 18 and an N-type emitter region 20 are formed in the field region to constitute a bipolar transistor. Polycrystalline silicon 17 within trench groove 12 is connected to collector region 8 .

'A P-type head region 22 and an N-type region 24 are further formed in the single crystal silicon film 8, and the region 24 is a drain.

N-channel M in which the region 22 is the channel region, the single crystal silicon film 8 is the source, the silicon oxide film 14 of the trench groove 10 is the gate oxide film, and the polycrystalline silicon 16 is the gate electrode.
An OS transistor is configured.

26 is an insulating film between the eyebrows; c, E: B, BG, D, and a are extraction electrodes for the collector, emitter, base, channel region, drain, and gate electrode, respectively. Illustration of the passivation film is omitted.

The collector of the bipolar transistor and the source of the MOS transistor share the same region of the single crystal silicon film 8.

In order to use the vertical N-channel MoS transistor as a load of the bipolar transistor in this embodiment, it is sufficient to connect it as shown in FIG. 2 or 3. FIG. 2 shows a case where the vertical N-channel MOS transistor is a depletion type, and FIG. 3 shows a case where the vertical N-channel MOS transistor is an enhancement type.

Next, the manufacturing method of this example will be explained with reference to FIG.

(A) Silicon substrate 2 is thermally oxidized to form silicon oxide film 4.

(B) A high melting point metal film 6 such as tungsten is deposited on the silicon oxide film 4 by sputtering and patterned by photolithography and etching.

(C) In order to form a single crystal silicon film on the silicon oxide film 4 and the high-melting point metal film 6, a polycrystalline silicon film 30 with a thickness of about 5,000 wafers is deposited by low pressure CVD, and silicon nitride After the film 34 is deposited by low pressure CVD, the surface is coated with polyethylene glycol 36 as a cooling medium.

After that, the beam 38 of an argon ion laser with an optical output of about 3 W is focused by a lens and irradiated onto the polycrystalline silicon film 30 to melt the polycrystalline silicon film 30, and by scanning the melted part, the single crystal silicon film 30 is heated. Forms a film.

(D) Polyethylene glycol 36 and silicon nitride film 34 are removed, and N-type impurities are introduced into the obtained single-crystal silicon film 8 to make it N-type.

(E) Base region 18 by normal bipolar process
, forming an emitter region 20. At this time, vertical M
A channel region 22 and a drain 24 of the OS transistor are formed in advance.

(F) Trench grooves 10 and 12 are formed in the element isolation region by dry etching. The trench groove 12 is formed at a position where the high melting point metal film 6 is exposed within the groove. trench groove 1
o is formed at a position where regions 22 and 24 appear on the wall surface.

By oxidizing, a silicon oxide film 14 is formed on the wall surface of the trench groove 10.12. The silicon oxide film 14 is made to have a thickness of about 1, for example, about 500, so that it can be used as a gate oxide film of a vertical MOS transistor. When an oxide film is formed on the surface of the high melting point metal film 6 within the trench groove 12.

It is removed by dry etching such as RIE.

(G) Deposit polycrystalline silicon so that the trench groove 10.12 is completely filled, and etch back to leave polycrystalline silicon 16°17 inside the trench groove 10.12. Polycrystalline silicon 16.17 has a low resistance. impurities such as phosphorus are deposited and thermally diffused.

After that, an insulating film 26 such as PSG is deposited, contact holes are formed, and metal wiring is used to take out the electrodes C, E, and B.
, BG, D, and G to form a passivation film.

The process of forming single crystal silicon film 8 will be explained in more detail.

Depositing an amorphous or polycrystalline silicon film, providing a cooling medium on the silicon film, irradiating the silicon film with an energy beam such as a laser beam to melt it, and growing crystals while moving the molten part. A single crystal silicon film 8 is thus obtained.

As the cooling medium, polyethylene glycol, polyethylene ether, etc., which are generally known as surfactants, are used.
Polyethylene ester, polypropylene oxide, etc. can be used.

In FIG. 4(C), a silicon oxide film 4 and a high melting point metal film 6 are shown.
A polycrystalline silicon film 30 is deposited thereon, a silicon nitride film 34 is deposited on the polycrystalline silicon film 30, and polyethylene glycol 36t is deposited as a cooling medium on the silicon nitride film 34.
i-Applying.

Another method is to deposit a silicon oxide film with a thickness of about 10000 on the silicon nitride film 34 on the polycrystalline silicon film 30, for example, by low-pressure CVD, coat it with polyethylene glycol 36, and then deposit polyethylene glycol 36 on top of it. An optical glass plate may be placed on the glycol 36.

The silicon oxide film is provided on the silicon nitride film because polyethylene glycol 36 has better wettability on the silicon oxide film than on the silicon nitride film 34.

The reason why the optical glass plate is placed on the polyethylene glycol 36 is to make the thickness of the polyethylene glycol 36 uniform.

(Effects of the Invention) In the present invention, a vertical MOS transistor is provided as a load of a bipolar transistor separated by a trench isolation method, and a high melting point metal film or a high melting point metal is provided under the bipolar transistor to take out the current of the bipolar transistor. Since the current of the bipolar transistor is taken out through the buried alloy film and the isolation trench, the bipolar transistor can operate faster than a bipolar transistor with a buried diffusion layer.

Further, since current is taken out from the bipolar transistor through the trench, the degree of integration of the semiconductor integrated circuit device can be further increased.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing one embodiment, FIGS. 2 and 3 are circuit diagrams showing connections of the same embodiment, and FIGS. 4(A) to 4(G) are manufacturing methods of one embodiment. FIG. 4...Silicon oxide film, 6...High melting point metal film. 8... Single crystal silicon film, 10.12...
...Trench groove, 14...Silicon oxide film, 1
6.17...Polycrystalline silicon, 18...
・Base region, 20...Emitter region, 22.
...Channel region, 24...Drain. Figure 2

Claims (1)

[Claims] (1) A single-crystal silicon film is formed on the insulator, and a bipolar transistor and a vertical MOS are installed in the field region separated by the trench isolation method of this single-crystal silicon film.
Transistors are formed by sharing some areas,
A refractory metal film or a refractory metal alloy film is embedded in the lower part of the bipolar transistor in the single crystal silicon film, and a conductor serving as a gate electrode of the vertical MOS transistor is embedded in the trench isolation groove; A semiconductor integrated circuit device in which a conductor is embedded in contact with a high melting point metal film or a high melting point metal alloy film.