JPS6188523A - Formation of electrode - Google Patents

Abstract

PURPOSE:To attach an electrode to an intermediate film of multilayer film by forming a connecting hole only to the electrode region, depositing an insulator thereto and forming an electrode through removal of insulator from the bottom surface of connecting hole. CONSTITUTION:A p type layer 11 is provided to a half-insulating GaAs substrate 10 and a gate electrode 15 and an SiO2 14 are also provided by stacking a GaAs 12 and an n type AlxGa1-xAs 13. An ohmic electrode can be attached to a p type layer 11 by providing a resist mask 16, etching it with an etchant of HF:NH4F=1:15 and thereafter etching AlxGa1-xAs, GaAs with the NH4OH system solution. Thereafter, a mask 16 is removed and the surface is covered with CVD SiO2 15. The anisotropic etching is carried out using a mixed gas of NF3 and N2 in the parallel plate type apparatus, leaving SiO2 17'' at the side wall of hole. An ohmic electrode of Cr-Au 18 is attached to the exposed hole bottom of substrate. This method is particularly suitable for formation of electrode to a specific layer in the epitaxial layers.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for forming an electrode, and particularly to an electrode forming method suitable for forming an electrode in a specific epitaxial layer in a multilayer epitaxial layer.

[Background of the invention]

In recent years, semiconductor devices (e.g., hetero-bipolar transistors; Japanese Patent Laid-Open No. 1983-1993) have been developed using epitaxial growth methods that are controllable at the single-atom level, such as molecular beam epitaxy (MBE) and metal-organic pyrolysis (OM-VPE).
-43583, selectively doped heterojunction field effect transistor; JP-A-55-132074, etc.) are being actively developed.

By the way, when creating devices using such multilayer films, electrodes are often used to achieve high integration, reduce parasitic capacitance and resistance of transistors, or improve flatness within the substrate. The structure and how to extract it are very important issues.

The main reason for this is that it becomes necessary to attach electrodes to parts other than the topmost film of the multilayer film, that is, to the film existing in the middle, to the part near the substrate, etc.

FIG. 1 shows an epitaxial layer for producing a hetero bipolar transistor. That is, semi-insulating G a A
Approximately 5000 n4 type GaAs layer I on s substrate B, 3000 n-GaAsR1111,100
The basic structure is 0 p-type G a As FJ II [, 2000 n-type A Qo, 3 G ao, , As layer ■. However, the above-mentioned film thickness indicates the value of a standard hetero bipolar transistor. The problem is that it is necessary to make ohmic contact to the n'' GaAs layer I, which is the collector layer, and to the p-type GaAs layer 2, which is the base layer.The problem is that the parasitic capacitance.

There was a need for a method for attaching electrodes that lowered parasitic resistance and did not impair in-plane flatness.

[Purpose of the invention]

An object of the present invention is to provide a method for selectively attaching electrodes to a plurality of overlapping semiconductor layers.

[Summary of the invention]

FIGS. 2a-2e show cross-sectional views of a multilayer film processing process for explaining the present invention. Here, an example will be shown in which among three layers 2, 3.4 having different properties on the substrate 1 as shown in FIG. 2a, an electrode is formed to connect only to the second layer.

4th. Contact holes 47 are formed by selectively etching the 3N layer or by removing the 3rd and 4th layers using an etching solution with a very slow etching rate.

Next, low pressure CV D (Che!lical V
aporDeρosition) method and thermal oxidation (especially S
The insulating material 5 is deposited on the side wall, the bottom surface, and the upper part of the fourth semiconductor layer of the contact hole using a method such as (effective in the case of (i)) (c).

Next, the oxide 5 on the bottom of the contact hole 47 is removed by anisotropic etching using the photoresist 6 and the like as a mask (d). Thereafter, after cleaning, electrode metal 7 is deposited to fill the contact hole (e). After the electrode metal 7 is deposited, depending on the material, some do not require alloying, while others require alloying (GaAs, etc.).

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail by describing examples in which the electrode forming method of the present invention is applied to various devices.

Example 1 A selectively doped heterostructure has a buried layer for controlling the threshold voltage of a junction FET, and FIG. 3(a) shows an example of the process when the present invention is implemented when an ohmic electrode is formed in the buried layer. - Shown in (e).

After forming the selectively formed p-wall region 11 in the semi-insulating GaAs substrate 10, impurities are not intentionally doped (undoped, the impurity level is approximately 10"aI+-").
The GaAs layer 12 has about 5,000 layers 1 and n-type AD,
G a, -, A s layers 13 were crystal grown by 500 people using the MBE (molecular beam epitaxy) method to form gate electrodes 1.
51 An interlayer insulating film 14 (CVDSiO, 1li) was formed (a).

To form an ohmic electrode on the P-type buried layer 11, using the photoresist 16 as a mask, etching is performed for 90 seconds with an etching solution containing a 1:15 mixture of hydrofluoric acid and ammonium fluoride, and then NH4OH-based Afl, Ga, - ,As,
GaAs etching solution (etching speed 250 people/w)
(b) Then, after removing the photoresist 16, it was etched with plasma CvD@2000.
(7) SiO2 was formed (c) 6 Next, the SiO2 on the bottom surface 17' of the contact hole 47 was selectively etched to form an electrode. For example, only the SiO2 at the bottom of the contact hole 47 can be selectively etched by etching using a mixed gas of NF, gas and N2 in a parallel plate etching device (d).

The important thing about this reactive ion etching is to set highly directional etching conditions to remove the S etching on the side wall of the contact hole.
It is to leave i0.17'. Next, 30% of Cr-Au 18 was added as an ohmic electrode metal to the p-wall region 11.
00 people formed. The plan view of the FET of this example is shown in Figure 3 (
Shown in f). The area of contact hole 18 is 3 μm in this case.
The width was 3 μm.

Embodiment 2 An embodiment in which the present invention is applied to the formation of a gate electrode of a selectively doped heterojunction type FET having a buried junction type gate is shown in FIGS. 4(a) and 4(b).

After forming the p-wall region 11 in the semi-finished GaAs substrate 10, undoped GaAs is formed using the OM-VPE method.
After growing layer 12 by 3000 people, n-type A Q −G a ,
- After forming the s layer 13'1500 layers, SiO2 is applied to the entire surface.
4 was formed by CVD method. Next, source/drain electrode 1
9.20 was formed (a). In the FET, which is characterized in that an ohmic electrode is attached to the p-wall region 11 and the two-dimensional electron gas layer 50 at the heterojunction interface is controlled by the junction between the undoped GaAs layer 12 and the p-wall region 11, as in the first embodiment. , it is necessary to form an ohmic electrode in the buried p-wall region 11. The specific electrode forming method is the same as in Example 1.

A feature of the electrode formation of the present invention is that the contact hole is formed only in the electrode region, and the electrode is formed with the semiconductor layer (13° 12 in Fig. 4) and the insulator left on the side wall, so that the semiconductor element It has excellent insulation properties and flatness between layers, and exhibits particularly excellent effects when applied to integrated circuits. The insulator 17 to be deposited on the contact hole is 5 inches.
In addition to 2, there are also Si31'J4. A Q, O,, A Q
N etc. can also be used.

Embodiment 3 An embodiment in which the present invention is applied to the formation of a base electrode of a hetero bipolar transistor is shown in FIGS. 5(a) to 5(d).

Using the OM VPE method on the semi-insulating GaAs substrate 10, 1×101
n-type GaAs layer 21 with a concentration of @rIrn-3
5,000 people. Next, the undoped GaAs layer 2
2 to form 3000 people, and Zn to I X I O1
1000 layers of GaAs layer 23 (base layer) containing a concentration of g+n-', and n-type AQ, Gal-, As layers (x-0, 3) containing 2 x 10" mm-3 of Se.
24. After forming 2,000 people, 2,000 people were coated on the entire surface using the CVD method.

Layer 25 was formed. In this implementation, only the base electrode forming process is shown. To form a base region, Si0
．． 25 is removed by dry etching. moreover,
A Q , Ga , , As layer 24 is Ga As
A Q-Gal-- is dry etched using a C22 plasma to selectively etch layer 23.
The As layer 24 was selectively removed. Subsequently, after removing the photoresist 16, 2000 Si0.27 layers were formed on the entire surface by CVD. Next, S on the bottom of this contact hole.
iO227' was selectively removed in the same manner as in Example 1, leaving 5 inches of 227' on the sides.

Continuing, Mg ions 23' were accelerated at an acceleration voltage of 100 kV.
Ion implantation was performed at a dose of X 10 "rm7". The photoresist 16' was removed and annealing was performed at 850° C. for 20 minutes in an As atmosphere. In this way, a p9 region 23' connected to the p-type base region 23 was formed. Subsequently, Cr-Au18 was formed to make an ohmic connection to this p3 region. , a method of diffusing a p-type dopant such as Zn may be used to form the P'' region 23'.

Embodiment 4 An example in which the present invention is applied to the formation of a drain electrode of an FET that extracts current in the direction perpendicular to the heterojunction interface from a two-dimensional carrier accumulated at the heterojunction interface is shown in FIGS. 6(a) to 6(a).
Shown in (e).

Semi-insulating GaA with n-type region 11 selectively in the substrate
A p-GaAs layer 26 (doping level is 101s uniformly 1 to 10" mm-3) is formed on the s-substrate 10 with a thickness of 1000 MB.
After the growth using the E method, 500 layers of n-type AQ, Gal-, As layers 24 containing I×10"+ny+-3 Si were grown. After forming the gate electrode 15, 2000 layers of CVD were grown.
S i○225 was deposited (a). A contact hole for forming an ohmic electrode is formed in the n-type buried layer 11' by the same method as in Example 1, and the drain metal 1 is
8'". In this case, for ohmic contact to n-type GaAs.

A u - G e / N i / Au 18"'
It was used. .

FIG. 6(c) shows a gate region 15 and a drain metal 11'.
, a plan view of the drain electrode 18 is shown.

In the above examples, G a As , A Q, G a,
, A s , and only an example in which the present invention is applied to a device using , A s, has been shown. However, the present invention is more effective when forming an electrode on an N3- epitaxial growth layer because a p(6) film can be used.InP, InGaA
It goes without saying that the present invention can also be applied to forming electrodes of devices using other compound semiconductors such as sP.

〔Effect of the invention〕

If the electrode forming method of the present invention is used, a contact hole is formed only in the electrode area, an insulating material is deposited, and the insulating material on the bottom of the contact hole is removed to form the electrode, so it has excellent flatness and is suitable for integrated circuits. A particularly suitable electrode can be formed.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a multilayer epitaxial layer for explaining the present invention in detail, Fig. 2 is a cross-sectional view showing the steps for explaining the electrode forming method of the present invention, and Figs. FIG. 2 is a cross-sectional view showing steps in an example and a plan view of an electrode forming part. 1... Substrate, 2... Semiconductor layer requiring electrode formation, 3.4... Other semiconductor layer, 47... Contact hole,
5%1 Figure %Z Figure 3 Figure Z 3 Country Figure 5 Figure 5/g

Claims (1)

[Claims] 1. In a semiconductor device having at least one type of semiconductor layer (II) on the semiconductor layer (I) on which an electrode is to be formed,
The semiconductor layer (II) in the electrode region is removed, an insulator is deposited on the removed region and a part of the upper part of the semiconductor layer (I), and the deposited insulator in contact with the semiconductor layer (I) in the electrode region is A method for forming an electrode on a semiconductor layer (I), characterized by selective removal.