JPH0246776A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the distribution of electron at an equi-energy surface where a conduction effect is large, to thin a silicon film, and decrease surface field effect, by making a specified tensile strain exist in a semiconductor region. CONSTITUTION:After a thick insulating film 2 is formed on a silicon (100) substrate 1, the insulating layer 2 is eliminated and a part of the (100) substrate 1 surface is exposed; thereon, a polycrystalline silicon layer 3 is deposited in a thickness equal to or less than, e.g., 1000Angstrom ; the polycrystalline silicon layer is turned into a single crystal silicon layer 5 by EB annealing or the like while the exposed silicon (100) substrate 1 is used as crystal species; in the single crystal silicon layer 5, tensile strain of 8.1X10<-4>-7.3X10<-3> is made to exist by, e.g., the following EB annealing conditions; electron beam current is 65-90mA, scanning speed is 10cm/sec or more, and the substrate temperature is 600 deg.C or less. After devices like storage elements are formed in the single crystal silicon layer 5, a thin SOI film is formed on the upper layer. A thickness range of 125-1050Angstrom is most suitable for the SOI film.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) This invention relates to semiconductor devices, particularly extremely thin 80I
The present invention relates to a field effect type MO8 semiconductor device using a substrate.

(Prior Art) First, let us consider the operation of a conventional field-effect MO8 transistor as a semiconductor device. FIG. 2 is a schematic diagram of a MOS transistor.

For example, in an n-channel MOS transistor, when a positive voltage is applied to its gate electrode, positively charged holes begin to be repelled by the positive voltage on the surface of the p-type semiconductor layer 2D under the gate, and their density decreases. Become.

Eventually, the holes are swept out and a space charge region (depletion layer) is formed. If you ask me more about this,
In a very thin region under the gate, p-type silicon converts to n-type (this is called inversion). This occurs as a result of the strong negative charge attracting negatively charged conduction electrons from the surroundings.

The attracted conduction electrons form an n-shaded region.

In the figure, (c) and (c) are the source and drain, respectively.

For example, when an n-channel MO8 type transistor is formed on a silicon (100) plane, conduction electrons in the inversion layer formed on the surface of the p shadow region under the gate due to input voltage are
Motion perpendicular to the surface is quantized. A schematic diagram of the isoenergetic surface (valley) of the conduction band of silicon is shown in FIG. The iso-energy surface can be expressed by the following equation (11).

(' * J : xs Y * z) (α: Band) (m: Rest quality of electron t) The mass of an electron is a function of E(lk) and can be expressed by the following equation (2).

From equations (1) and (2) above, when considering the movement of electrons in the inversion layer in a direction perpendicular to the surface, electrons are lighter in valleys on the x and y axes, and heavier in valleys on the z axis. . According to conventional calculation results, the mass m6 of a heavy electron is m,=0.
98rr%, light electron quality 11m1 is m, = 0.1
It is said to be 9-. Here is the rest mass of the rnoVi electron. Therefore, in the MO8 element on the (100) plane, the valleys in the direction perpendicular to the surface are at a low energy level, and these electrons are utilized for conduction phenomena.

By the way, let us consider the operation of this n-channel MOS transistor. Voltage V between source and drain electrodes
d is applied, vg is applied, and the conduction electrons in the inversion layer become y
m when moving in the direction.

From Equation (2), since there are almost only two-axis valleys after the start of inversion, the mass of the electron is nl9, and the mobility μ of the electron can be expressed by Equation (3).

μ=(eτ)/mt (3) τ: Relaxation time due to scattering Therefore, if only the influence of mass is considered, μ should be large for light electrons. However, in the conventional MO8 element,
Apart from the effect of m, the decrease due to τ has a large influence. That is, by applying Vg to form an inversion layer, a strong electric field is formed near the surface, and the electron mobility is affected by surface scattering, and near the strong inversion layer (
3) τ in the equation decreases and μ becomes smaller. That is, there is a problem in that even though electrons with a light mass are prepared, a sufficient improvement in the mobility μ cannot be expected due to the effect of τ, that is, the relaxation time due to scattering.

(Problems to be Solved by the Invention) The present invention solves the above-mentioned conventional problems, and by incorporating internal pressure strain in the silicon film forming the semiconductor device, electrons in valleys with a large conduction effect are In addition to increasing the distribution, the silicon film thickness is kept thin to reduce the surface field effect, thereby creating a semiconductor with high mobility and large drive ability that can obtain a sufficiently large current even in the weak gate electric field region. The purpose is to provide equipment.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention provides (100) a source and a drain containing an n-type impurity in a p-type silicon semiconductor region, and a source and a drain on the semiconductor region between the source and the drain. In the semiconductor device in which a gate electrode is formed through an insulating film in the semiconductor region, 8. lX10'~7.3X10
To provide a semiconductor device characterized in that it has an inherent tensile strain of No. 3.

(Function) According to the present invention, in a silicon (100) substrate, 2
A compressive stress of about 10 dyne/cj is generated in the direction, and as a result, the valley (equal energy surface) of conduction electrons changes as shown in FIG. That is, the energy of the ballet on the two axes decreases, and the equal energy surface expands. and,
When tensile stress is applied in the x and y directions, the energy of the valley on the D, Xl and Y axes increases, and the iso-energy surface becomes smaller. In this way, the probability of the existence of electrons is 90 or more, with the valley on the z-axis being the highest.

When Vg is applied in this state, as 7g increases, the conduction band edge energy ■ approaches the Fermi level EF, conduction electrons are induced on the silicon (100) surface, and the p-type semiconductor is inverted to the n-type. Considering the motion in the y-axis direction, the above (1
) ~ (3) These electrons are light electrons, and the mobility of electrons between the source and drain is extremely large because most of them are light electrons.

Next, let's consider the effect of the surface electric field.

Even if Vg does not bring it to the strong inversion region, the energy valley in the 11Cz direction is already low in energy due to strain, as described above.

Furthermore, by thinning the SOI film on which the semiconductor device is formed, the depletion layer is created even within the SiO layer, and the vertical electric field of the surface inversion layer is made extremely small.
This makes it possible to provide an element with extremely high mobility even in the weak inversion region.

(Example) An example according to the present invention will be described in detail using the drawings. FIG. 4 is a process sectional view showing an embodiment method for obtaining an embodiment according to the present invention.

First, as shown in FIG. 4(a), the underlying silicon (10
0) After forming a thick insulating film layer (2) on the substrate (11), the insulating film layer (2) is removed (Zoo) to expose a part of the surface of the substrate (1). A polycrystalline silicon layer is formed on this. Alternatively, an amorphous silicon layer (3) is deposited to a thickness of, for example, 100 OA or less.Next, using the exposed silicon (ZOO) substrate [1) as a crystal seed, multiple layers are formed by EB annealing or laser annealing. Crystalline silicon layer or amorphous silicon layer or single crystal silicon layer (
5) (Fig. 4(b)). Here, for example, as a condition for EB annealing, one electron beam current is 65 to 90 mA1.
Scanning speed is 10LM/sec or more, substrate temperature is 600℃
By setting the following appropriate conditions, it is possible to create a tensile strain of 8.1X10 to 7.3X10 in the single crystal silicon layer (5).

In this example, the electron beam current g Q m Ar scanning speed was 15α/, and the substrate temperature was 550°C. As a result, in the thermal process during single crystallization, the upper silicon layer (5
) and the lower insulating film layer (2), the upper silicon layer (5) has a tensile strain in the xx and yy force directions of approximately 10 after cooling, which is converted into stress of 10 d.
It corresponds to about yne/-. This upper silicon layer (5)
A transistor (7) including source, drain and channel regions is formed (Fig. 4(C)).
).

Here, after forming a device such as a memory on the single crystal silicon layer (5), a thin SOI film may be formed as an upper layer.

Furthermore, other MOS transistors may be formed in addition to the above-mentioned MOS transistors to form a multilayer structure, or they may be formed in combination with npn transistors and the like.

Furthermore, as another embodiment according to the present invention, (ioo
) When packaging a memory or the like that includes an n-channel MOS transistor formed in a p-type nested crystalline silicon semiconductor film, the claws aυ of the package come into contact with the four corners of the chip Ql as shown in Figure 5. 8. on the semiconductor film. A stress that causes a tensile strain of 1×10 to 7.3×10” may be applied.

In the embodiment according to the present invention, even in the weak inversion region, the mobility is 23
00 d/Vsee could be obtained. This value is 550, which is the value of the conventional (7) n f-y channel M OS element.
It was found that the increase was approximately four times that of CDI/Vsee.

Furthermore, the SOI film had the best mobility in the range of 125 to 1050 A, and high mobility was obtained.

〔Effect of the invention〕

According to the present invention, a semiconductor device having high mobility and large drive power can be obtained.

[Brief explanation of the drawing]

Figure 1 shows the isoenergetic surface (valley) of the silicon conduction band.
FIG. 2 is an explanatory diagram for explaining the MOS transistor embodiment. 1... Silicon (100) substrate, 2... Insulating film, 3
...Polycrystalline or amorphous silicon layer, 4...
・Crystal seed, 5... Single crystal silicon film. Agent Patent Attorney Nori Ken Yudo Matsuyama Hikaru No.

Claims (2)

[Claims] (1) (100) A semiconductor device including a source and a drain containing n-type impurities in a P-type silicon semiconductor region, and a gate electrode formed on the semiconductor region between the source and the drain via an insulating film, wherein the semiconductor The area includes 8.
A semiconductor device characterized by having an inherent tensile strain of 1×10^-^4 to 7.3×10^-^3. (2) The film thickness of the semiconductor region is 125 Å to 1050 Å
The semiconductor device according to claim 1, characterized in that: