JPH0246967B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a high-speed input/output processing method, and particularly when inputting and outputting large amounts of data, it does not use an input/output buffer and moreover, it It relates to a device that speeds up input and output by performing input and output in parallel.

[Prior art and problems]

For example, in input/output processing in FORTRAN,
As shown in FIG. 1, when data stored in the main storage device 1 is stored in the DASD 3, an input/output buffer 2 is provided.
Temporarily hold the data transferred from
It was stored on DASD3. With this method, if the amount of data to be processed is huge, the number of data transfers from the main memory device 1 to the input/output buffer 2 will be extremely large, and read/write commands will have to be issued each time. Since input and output must be performed, there is a problem in that it takes a very long time to store the data.

For this reason, conventionally the buffer was set to 2-1 and 2-1.
Transfer speed has been increased through parallel processing in which a plurality of DASD devices 3-1 and 3-2 are provided, data is blocked, and data is transferred in parallel to a plurality of DASD devices 3-1 and 3-2. In this case, the data is divided into blocks as shown in Figure 1.
Blocks are not stored sequentially in the DASD devices 3-1 and 3-2, but blocks 1, 3, . . . are stored in the DASD device 3-1, and blocks 2, 4, . . . are stored in the DASD device 3-2. is stored.

In either case, it is necessary to hold the transferred data in a buffer, so in order to increase the speed, a very large input/output buffer is required.
When using the main storage area as this input/output buffer, not only a large main storage area is required for the input/output buffer, but also the transfer time between the data area in the main storage area and the input/output buffer is extremely long. It becomes something big.

Furthermore, if the amount of data input/output at one time is larger than the input/output buffer, providing the input/output buffer becomes meaningless.

[Purpose of the invention]

The purpose of the present invention is to solve these problems by providing a high-speed system that enables direct data transfer between an input/output device and a specified array data area without using an input/output buffer. The purpose is to provide an input/output processing method.

[Structure of the invention]

In order to achieve this object, the high-speed input/output processing method of the present invention provides a command generation section and a parallel processing control section in a data processing device having a central processing unit, a main storage device, and a plurality of direct access storage devices. , data is stored in the main memory in blocks with the maximum block length of the direct access storage device, and the command generation unit writes the storage destination of the input/output data and the command assigned with the storage destination of the data to each direct access storage device. The invention is characterized in that, based on the commands, the parallel processing control unit performs input/output control of data to a plurality of direct access storage devices in parallel based on the blocks.

[Embodiments of the invention]

An embodiment of the present invention will be described based on FIGS. 2 to 6.

2 and 3 are functional configuration diagrams of the present invention, FIG. 4 is a configuration diagram of an embodiment of the present invention, FIG. 5 is a flowchart, and FIG. 6 is a diagram explanatory of the operation of the present invention.

In the figure, 4-1 to 4-m are CCW creation units, 5 is a parallel file access control unit, 10 is a main storage device, 11 is a CPU, 12 is a command creation unit,
13 is a parallel file access control unit; 1
4 is a channel processor, 15-1, 15-2
are channels, 16-1 to 16-m are data control units, and 17-1 to 17-m are direct access storage devices (hereinafter referred to as DASD).

Before describing the present invention in detail based on one embodiment, its outline will be explained with reference to FIGS. 2 and 3.

As shown in FIG. 2, the input/output data arranged in the main storage area for storage in the DASDs 3-1, 3-m is divided into blocks 1, 2, . . ., N. The block length of blocks 1, 2...N is DASD3-1~
3-m maximum block length. here
The maximum block length of the DASDs 3-1 to 3-m is usually the byte length that can be stored continuously in one cylinder, and is determined based on the DASDs 3-1 to 3-m. Then, block 1 is assigned to write on DASD 3-1, and block 2 is assigned to write on DASD 3-1.
Assign it to fill in 2, and do the same below.
Allocate data so that each block is sequentially stored on DASD3-m. Next, block m+1 is DASD3
-1, block m+2 is assigned to DASD 3-2, and in this way all blocks up to block N are assigned to DASD 3-1 to DASD 3-m.
Then, CCW1 to CCWm are created for each DASD 3-1 to 3-m according to the assignment. Therefore
CCW1 created for DASD3-1 has
The starting address in the main storage area of block 1, block m+1, . . . to be written to DASD 3-1, the transfer byte length of one block, the write command, etc. are entered. In this way, CCW1~
CCWm is assembled.

Before assembling this CCW, each DASD3
In order to establish usage rights for -1 to 3-m, DASD open processing is performed on the host, and each
Establish usage rights for DASD3-1 to 3-m. At this time, the data control blocks for each DASD 3-1 to 3-m are referenced to obtain access information indicating from where on each DASD data can be set.

Therefore, based on this access information regarding each DASD 3-1 to 3-m and the above CCW1 to CCWm, each DASD 3-1 to 3-m is supported.
EXCP is created. This EXCP includes instruction codes such as read and write, the start address of blocks 1 to n, the access destination address to DASD3-1 to 3-m, the transfer byte length, etc. Data is transferred one block at a time from -1 to 3-m. When the transfer of one block is completed, the next EXCP is sent,
The second block will be transferred to DASDs 3-1 to 3-m.

In this case, data transfer to the DASDs 3-1 to 3-2... is carried out by the parallel file access control unit 5 as shown in FIG.
1 to 3-3 (FIG. 3 shows an example of three DASDs) in parallel.

Next, one embodiment of the present invention will be described with reference to FIGS. 4 to 6, with reference to other figures as necessary.

In FIG. 4, the command creation section 12 is
EXCP is created using CCW1 to CCWm.

The main storage device 10 includes DASD 17-1 to 17-
The data to be transferred is stored in m.

(1) As shown in FIG. 5, the input/output statement that should now transfer this transfer data in the main storage device 10 to the DASD 17-1 to 17-m (read/write command and the address and size of the transfer data are specified) is the CPU
11, the CPU 11 analyzes the data and divides the transferred data (data items) into the block lengths of the DASDs 17-1 to 17-m to form blocks 1 to n. Then, based on the start address of the transfer data, (2) When the transfer data is divided into blocks 1 to n in (1) above, multi-open processing is performed for the DASDs 17-1 to 17-m, and each DASD
Access destination addresses for 17-1 to 17-m are obtained, and these are also accessed by the command creation unit 12.
transmitted to.

(3) The command creation unit 12 writes each DASD 17-
Access destination addresses for 1 to 17-m,
Blocks 1 to 1 shown in CCW1 to CCWm above
Depending on the start address of n and the execution instruction code,
Each DASD17-1 to 17-m
Create EXCP1 to EXCPm and use this channel.
The data is sent to the processor 14. and each DASD1
A multi-WAIT is issued so that the processes of 7-1 to 17-m are completed in synchronization. As shown in Fig. 6, in addition to the instruction command and the data length of one transfer, the block 1...P... to be transferred to DASD1 is written in EXCP1. 16-1
can sequentially control the transfer of blocks 1...P... from the main storage device 10 to the DASD 17-1, and similarly can control the transfer of blocks 1...P... from the main storage device 10 to the DASD 17-1.
16-m are also each EXCP2... EXCPm causes each DASD 17-
2...It is possible to sequentially control the transfer of blocks to be transferred to 17-m. In this case, EXCP1
~ After receiving EXCPm, each DASD control device 16-1 to 16-m will operate in parallel, so the huge transfer data prepared in the main storage device 10 will be transferred to the DASD 17-1 in a short time. ~17
-m will be forwarded and processed.

If the data to be transferred prepared in the main storage device 10 is not huge, such as several tens of gigabytes, but is of normal size, and it is preferable to transfer it using the same method as before, use this device. It is sufficient to operate in normal transfer processing mode. In that case, the CCW output from the CPU 11 is sent to the channel processor 14, so that normal transfer control, such as using a part of the main storage device 10 as an input/output buffer, can be performed. Can be done.

Moreover, in the present invention, multiple array data distributed on the main memory can be treated as if they were a single array data, which means that data can be scheduled, and there is no need to combine distributed data into one, making it more efficient. It is also possible to output data length and issue timing signals in a manner that takes the device into consideration, that is, to avoid waiting for rotation.

〔Effect of the invention〕

According to the present invention, when transferring a huge amount of data, input/output can be performed directly between array data and an input/output device without using an input/output buffer for the input/output device, and a large amount of data can be transferred. By processing the data in parallel to a plurality of input/output devices, it is possible to speed up the input/output processing.

Moreover, since the block length of the block is set to the maximum block length of the direct access storage device, that is, the maximum transferable block length, data can be transferred efficiently. Scheduling is also possible, so distributed data can be processed efficiently.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the conventional input/output control state of array data, Figs. 2 and 3 are explanatory diagrams of the functional configuration of the present invention, Fig. 4 is a configuration diagram of an embodiment of the present invention, and Fig. 5 is a flowchart. FIG. 6 is an explanatory diagram of the operation of the present invention. In the figure, 4-1 to 4-m are CCW creation units, 5 is a parallel file access control unit, 10 is a main storage device, 11 is a CPU, 12 is a command creation unit,
13 is a parallel file access control unit; 1
4 is a channel processor, 15-1, 15-2
are channels, 16-1 to 16-m are dual control units, and 17-1 to 17-m are direct access storage devices.

Claims (1)

[Claims] 1. In a data processing device having a central processing unit, a main storage device, and a plurality of direct access storage devices,
In addition to providing a command generation section and a parallel processing control section, data is stored in the main memory in a plurality of blocks having the maximum block length of the direct access storage device, and a storage destination for data input and output by the command generation section is provided. A command with a storage location for the data is created for each direct access storage device, and based on the command, the parallel processing control unit performs input/output control of data to multiple direct access storage devices in parallel based on the blocks. A high-speed input/output processing method characterized by: