JPH0247080U - - Google Patents
Info
- Publication number
- JPH0247080U JPH0247080U JP12644988U JP12644988U JPH0247080U JP H0247080 U JPH0247080 U JP H0247080U JP 12644988 U JP12644988 U JP 12644988U JP 12644988 U JP12644988 U JP 12644988U JP H0247080 U JPH0247080 U JP H0247080U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- circuit element
- passive circuit
- hybrid integrated
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Casings For Electric Apparatus (AREA)
Description
第１図は本考案の一実施例を示す混成集積回路
装置の部品搭載図、第２図は従来の混成集積回路
装置の部品搭載図である。
１……外部リード端子、２……ボンデイング・
ワイヤー、３……配線基板、４……配線導体、５
……チツプ・コンデンサ、６……チツプ抵抗。
FIG. 1 is a component mounting diagram of a hybrid integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a component mounting diagram of a conventional hybrid integrated circuit device. 1...External lead terminal, 2...Bonding/
Wire, 3... Wiring board, 4... Wiring conductor, 5
...Chip capacitor, 6...Chip resistor.
Claims (1)
る配線基板と、外部リード端子間にまたがるよう
にリード短絡片上に直接搭載される受動回路素子
と、前記受動回路素子を半導体チツプと共に被覆
するモールド封樹脂膜とを含むことを特徴とする
混成集積回路装置。 A wiring board that is placed on a pedestal and has a semiconductor chip mounted on its top surface, a passive circuit element that is mounted directly on the lead shorting piece so as to span between external lead terminals, and a molded seal that covers the passive circuit element together with the semiconductor chip. A hybrid integrated circuit device comprising a resin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12644988U JPH0247080U (en) | 1988-09-27 | 1988-09-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12644988U JPH0247080U (en) | 1988-09-27 | 1988-09-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0247080U true JPH0247080U (en) | 1990-03-30 |
Family
ID=31377985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12644988U Pending JPH0247080U (en) | 1988-09-27 | 1988-09-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0247080U (en) |
-
1988
- 1988-09-27 JP JP12644988U patent/JPH0247080U/ja active Pending
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