JPH0247911B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field> The present invention provides a method for determining the number of output pixels relative to the number of pixels of an original image.
The present invention relates to an image processing apparatus that performs conversion processing by a factor of 2 ^M /2n+1 (M, where n is a positive integer), and particularly relates to an image processing apparatus that performs the conversion processing using an adder and a selector.

<Description of Prior Art> Conventionally, when the magnification ratio of the number of recording pixels to the number of original pixels in the main scanning direction or sub-scanning direction of a recording means is expressed by N (N is a positive integer),
For example, as shown in Utility Model Publication No. 58-27590,
The same original pixel may be used as a recording pixel N times in the main scanning and sub-scanning directions. Further, when the magnification ratio is expressed as 1/N, only one of the N original pixels may be used as a recording pixel.

However, if the magnification ratio cannot be expressed as N or 1/N, it is impossible to use the original pixels as they are as recording pixels, and special operations such as division are required. Therefore, in order to realize this, a complicated circuit is required.

<Purpose of the Invention> In view of the drawbacks of the conventional example described above, the present invention has been proposed to calculate the value of an output pixel using an adder and a selector when the magnification ratio is 2 ^M /2n + 1 (M and n are positive integers) which cannot be expressed as an integer ratio. The object of the present invention is to provide an image processing device which has a simple circuit configuration and can faithfully obtain original image information.

<Description of Examples> An example of conversion when the magnification ratio is set to 4/3 will be shown using FIG. 1.

In the figure, α indicates the main scanning direction of a recording device (not shown). A, B, C, and D are original pixels a, b, and
It has pixel levels c and d. A, B, C, D, and H are recording pixels.

Recording pixel A corresponds to the same position as original pixel A, so the pixel level is a. Recording pixel B, when the distance from original pixel B is 1, the distance from original pixel A is 3, so the pixel level is a and b. The weighted average value of 1:3 is a+3b/4. Recording pixel C is located between original pixels B and C, so the pixel level is b+c/2, and recording pixel D has a distance of 1 from original pixel C. Since the distance from the original pixel d is 3, the pixel level is 3c + d/4, which is the weighted average of c and d at a ratio of 3:1, and the pixel level of the recording pixel E corresponding to the same position as the original pixel D is d. . By repeating the cycle T in the figure, the pixel levels of all recorded pixels can be found. In this way, three original pixels can be converted into four recording pixels, and if recording is performed at the same recording density as when the original pixels are recorded as recording pixels, there will be four recording pixels in the main scanning direction. /You can get 3 times more images. Similar processing is also possible in the sub-scanning direction.

FIG. 2 shows a concrete circuit for converting three original pixels into four recording pixels. It is assumed that the pixel levels of the original pixels and recorded pixels are represented by 8-bit digital values. X and Y are 8-bit digital values of input original pixels, and both pixels are adjacent in the main scanning direction. Z is the output digital value of the interpolated recording pixel.

In the figure, 1 is a selector that selects and outputs either X or Y, 2, 3, 4, and 5 are 4-bit adders with input terminals _A1 to _A4 , _B1 to _B4 , and output terminals _S1 to S. _Four ,
and carry input terminal Cin, carry output terminal
Has Cout. 6 is a selector for selecting one of the inputs X, Y, V, W, 7 is line memory, ta, tb
is a switching timing signal for selectors 1 and 6.

In addition, selector 1 uses two CD4019s manufactured by RCA, and adders 2 to 5 are CD4008s manufactured by RCA.
Further, the selector 6 can be constructed by using four CD4052 manufactured by the same company.

Hereinafter, the circuit operation will be sequentially explained.

(1) The current value of X is a in Figure 1, and the value of Y is b in Figure 1.
Then, the selector 6 outputs X, that is, a as Z. This output is stored in line memory 7.

(2) Next, adders 2 and 3 both operate as 8-bit adders and perform the a+b operation. Of the outputs, the least significant bit (Si of counter 2) is not used (shifted by 1 bit), so the outputs of adders 2 and 3 become a+b/2. a+b/2 is input to one of adders 4 and 5. Since selector 1 selects Y at this time, adder 4,
5 performs the calculation a+b/2+b. Then, like adders 2 and 3, adders 4 and 5 do not output their least significant bits, so the output becomes a+3b/4, and selector 6 selects input W and stores it in line memory 7.

(3) Next, the value of input X becomes b, and the value of input Y becomes c
becomes. Then, the adders 2 and 3 perform the calculation of b+c/2 as described above, and the selector 6 selects the input V and stores the value of b+c/2 in the line memory 7.

(4) Next, the value of input X becomes c, and the value of input Y becomes d
becomes. Adders 2 and 3 then perform the calculation c+d/2, and the output thereof is input to adders 4 and 5. Adders 4 and 5 select c selected by selector 1.
and c+d/2 are added, and the value 3c+d/4 is finally input to the input W of the selector 6, which selects the input W and stores 3c+d/4 in the line memory 7.

By repeating the operations (1) to (4) above, it is possible to convert original pixels to recording pixels when the magnification ratio is 4/3. Figure 3 is a timing diagram of Figure 2, including the X and Y values at each timing, the selection inputs of selectors 1 and 6, the timing signals Ta and Tb, and the clocks C1 and CK2 for forming the timing signals Ta and Tb. It shows. Those skilled in the art can easily form such timing signals Ta and Tb from the clocks CK1 and CK2.

The data stored in the line memory 7 is transferred to the recording device for each main scanning line, for example.

The above has been described for the case of a magnification ratio of 4/3, but
Magnification ratio is 2/3, 8/3, 16/3, 2/5, 4/
5, 8/5, 16/5, 2/7, 4/7, 8/7,
Even in the case of 16/7 etc., recording pixels can be found by using the bit shift method and an adder.
In other words, if the magnification ratio is 2 ^M /2n + 1, where M and n are positive integers, it is possible to convert the digital value of the original pixel to the digital value of the recording pixel by using an adder and bit shift. .

FIG. 4 shows an example where the magnification ratio is 8/7. In the figure, A', B'..., H' are original pixels, and their pixel levels are a', b',..., h', and A', B',..., R'
are recording pixels, and each is converted to a pixel level as shown at the right end of the figure. 4/3 in case of 8/7
It is sufficient to form 1/8 of the information by performing one more bit shift operation than in the case of . In other words, it is sufficient to perform the shift operation the same number of times as M.

<Explanation of effects> As explained above, according to the present invention, the original pixel is 2 ^M /
Conversion to 2n+1 (M, n is a positive integer) times, i.e.
Conversion to a magnification that is not an integer ratio can be performed with a simple circuit configuration consisting of an adder and a selector without using a special arithmetic unit such as a divider, and the input digital amount is used as a part of the converted pixel. Enables scaling processing that is faithful to the original image information.

[Brief explanation of the drawing]

Figure 1 is an explanatory diagram of pixel conversion when the magnification ratio is 4/3, Figure 2 is a circuit diagram for performing the pixel conversion of Figure 1, Figure 3 is a timing diagram of each part of Figure 2, and 4
The figure is an explanatory diagram of pixel conversion when the magnification ratio is 8/7. In the figure, 1 and 6 are selectors, 2, 3, 4, 5
indicate a 4-bit adder, respectively.

Claims (1)

[Scope of Claims] 1. An image processing device that converts the number of output pixels relative to original pixels in the main scanning or sub-scanning direction by 2 ^M /2n+1 (M and n are positive integers), which an input means for inputting a digital amount of a plurality of pixels continuous in a direction; and an input means for adding the input digital amounts of a plurality of pixels;
a first adder that bit-shifts the addition result and outputs it as a 1/2 digital amount; and a first adder that adds the digital amount input by the input means and the output from the first adder, and bit-shifts the addition result. a second adder that outputs a 1/2-fold digital amount; and selecting the digital amount input by the input means and the digital amount from the first or second adder according to the pixel position after conversion. An image processing apparatus comprising: a selection means; and an output means for outputting the digital quantity selected by the selection means as a digital quantity of a converted pixel.