JPH0248725A - storage controller - Google Patents

Abstract

PURPOSE:To shorten a data storage processing time for a track buffer memory by means of the control of a micro code by setting optional values to address pointers as the result of the comparison of the values of the address pointers and the optional values which have previously been given. CONSTITUTION:When the address of the track buffer memory 10 coincides with the previously given value in an address comparison circuit 4 in the middle of transferring data from the track buffer memory 10 to a disk device, the values of the address pointers 2, 3 and 5 are set to the optional values. Since data stored in the continuous and optional address areas in the track buffer memory 10 can repeatedly be transmitted, data for one track is eliminated from being stored in the track buffer memory 10 by the control of the micro code. Thus, the data storage time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage control device, and in particular, to a storage control device suitable for processing to transfer continuous repetitive pattern data to a lower storage device without requiring intervention of a CPU. Regarding a control device.

[Conventional technology]

It is known that a buffer memory is used as a data transfer circuit that transfers data between a CPU and an external storage device, as proposed in Japanese Utility Model Application Publication No. 59-169632. For this purpose, there is a method of automatically incrementing the address by one each time one word of data transfer is completed, as proposed in Japanese Utility Model Application Publication No. 58-97661.

[Problem to be solved by the invention]

For example, when the external storage device is a disk device, with the recent increase in capacity and the high functionality of disk control devices,
It is conceivable that a track buffer memory having a capacity for one track is provided inside the disk control device, and the disk control device itself uses the data stored in the track buffer memory.

Against this background, one of the ways to improve the functionality of disk control devices is to enable the disk control device itself to verify its recording and playback characteristics against lower disk devices without requiring data transfer from the upper CPU. When writing continuous repeating pattern data for characteristic verification to the entire area of one track, a microcode control section inside the disk controller stores one track's worth of write data in the track buffer memory and writes it to the disk. There is a process to transfer it to the device.

At this time, there is a problem in the processing time required by the microcode to store one track's worth of data, which has been increased in capacity, in the track buffer memory under microcode control, resulting in an increase in processing time for verifying recording and reproducing characteristics.

An object of the present invention is to transfer data to a track buffer memory under microcode control of a disk controller when the disk controller itself transfers continuous repetitive pattern data to the disk device without the need for transfer with the CPU. The purpose is to shorten storage processing time.

[Means to solve the problem]

The above object is achieved by providing an address comparison section that compares the value of the address pointer with an arbitrary value given in advance, and means for setting an arbitrary value in the address pointer based on the comparison result of the address comparison section.

[Effect]

During data transfer from the track buffer memory to the disk device, if the address of the track buffer memory matches a predetermined value, the value of the address pointer is set to an arbitrary value. As a result, the data stored in any continuous address area in the track buffer memory can be sent repeatedly, so it is no longer necessary to store one track's worth of data in the track buffer memory under microcode control. Storage time can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3.

FIG. 1 is a block diagram of a data transfer section of a disk control device showing an embodiment of the present invention. Transfer control unit 1. Address pointers 2, 3 and 5. Registers 12 and 13. Address comparison circuit 42 selection circuit 6°7 and 9. data register 8
and 11. It has a track buffer memory 10.

Prior to explaining the present invention, a normal write operation between an upper CPU (not shown) and a lower disk device (not shown) will be explained.

When preparing for a write operation, the transfer control section 1 sets the data storage start address value in the track buffer memory lo to the address pointer 2 indicating the storage address via the data line 21. Similarly, a data extraction start address value is set in the address pointer 3 indicating the extraction address via the data line 21.

For ease of explanation, address pointer 2.3 is used here.
Both are set to zero.

During write operation, write data from the CPU is sent to data line 7.
1 to the selection circuit 7 using the control line 61 as its timing signal. During a write operation, write data is output to the data line 24 via the selection line 31. The transfer control unit 1 transfers the control line 41 according to the timing signal of the control line 61.
The contents of the data line 24 are set in the data register 8.

Here, the selection circuit 9 is set to output the contents of the data line 25 to the data line 26 via the selection line 32, and the write data is supplied as an input to the track buffer memory 10. The data line 27, which is the output of the track buffer memory 10, is set in the data register 11 by the control signal 47 and transferred to the lower disk device via the data line 73.

At this time, the transfer control unit 1 considers the time relationship between the control line 61 and the control line 62 which is the data transfer timing signal from the disk device, and selects the address pointer 2 by the selection line 33.
Address line 51 or address pointer 3 which is the output of
One of the address lines 52 which is the output of is outputted via the selection circuit 6 to the address line 54 which indicates the address of the track buffer memory 10. Furthermore, the control line 42 instructs the operation of storing data into the track buffer memory 1o, and the control line 47 instructs the extraction of data from the track buffer memory 10.

Note that address pointers 2 and 3 are connected to control lines 43 and 44.
are incremented by one each.

Although not shown, the end of data transfer can be recognized by counting the number of data transfer bytes.

FIG. 2 shows the timing of the above normal write operation.

Next, regarding the read operation, read data is transferred from the lower disk device via the data line 72 in FIG. be transferred.

Next, regarding the present invention, an operation in which the disk control device itself transfers continuous repeating pattern data to a lower disk device without performing data transfer with the CPU will be described with reference to FIG.

As a specific example, byte A' is stored at address '4', byte B' is stored at address '5', and byte C' is stored at address '6' in the track buffer memory 10 in FIG.
The case where the pattern ABC' is repeated and transferred to the disk device will be explained.

When preparing for transfer, the transfer control section 1 sets the storage start address '4' in the track buffer memory 10 in the address pointer 5 via the data line 21.

Next, the control line 32 instructs the selection circuit 9 to select the data line 21 as its output data line 26, and the control line 33 instructs the selection circuit 6 to select the address pointer 5 on the address line 54. An instruction is given to select the address line 53 which is the output.

In this state, the transfer control unit 1 controls #4 via the data line 21.
2, the byte A is stored in the track buffer memory 10.
′ is stored. Next, the value of the address pointer 5 is incremented by one to 5' using the control line 48, and then byte B' is stored in the track buffer memory 10 via the data line 21 and the control line 42. Thereafter, byte C' is similarly stored in track buffer memory 10 with the value of address pointer 5 set to 6'.

Next, the transfer control unit 1 transfers AB stored in the track buffer memory 10 to the register 12 via the data line 21.
Set the start address ``4'' of pattern data of C'. Set the address ``6'' of the rear end of the ``ABC'' pattern data in the register 13.

Next, the data extraction start address from the track buffer memory 10 is sent to the address pointer 3 via the data line 21.
Set to . For the sake of explanation, this value is assumed to be 4'.

When transferring data from the track buffer memory 10 to the lower disk device, the transfer control section 1 enables the address comparison circuit 4 via the control line 46. Further, the control line 33 instructs the selection circuit 6 to always select the address line 52, which is the output of the address pointer 3, as the address line 54, which is the output thereof.

In response to the control line 62, which is a data transfer timing signal from the lower disk device, the transfer control unit 1 extracts data from the track buffer memory 10 via the control line 47, and transfers the address pointer 3 to the address pointer 3 via the control line 44 every time one unit of data is extracted. Increment the value by one.

When the value ``6'' of the data line 23, which is the output of the register 13, and the value of the address line 52, which is the output of the address pointer 3, are equal, the address comparison circuit 4 sends a signal to that effect to the control line 45.
The address pointer 3 is notified by.

When the address pointer 3 recognizes by the control line 45 that the value of the address line 52 has become equal to the value ``6'' of the data line 23, the address pointer 3 changes the value of the register 12 by the next increment instruction of the control line 44. 4' to data line 2
2 and set it to yourself.

In the manner described above, data transfer from address 4' in track buffer memory 10 is performed again.

By repeating the above operations, the data of the "ABC" pattern in the track buffer memory 10 is continuously and repeatedly transferred to the disk device. The timing of this operation is shown in FIG.

〔Effect of the invention〕

According to the present invention, by providing a comparison section that compares the value of the address pointer with a value given in advance, and means for setting an arbitrary value to the address pointer based on the comparison result of the address comparison section, the track buffer memory can be stored. Since any data stored in the disk can be transferred continuously and repeatedly, it is possible to transfer a repeating pattern of data over the entire track to a lower disk device without the need for data transfer from the CPU by the disk controller itself. Therefore, it is not necessary for the transfer control unit to store data in the track buffer memory for all of one track, but only for the basic pattern that is repeated.

That is, there is an effect of shortening the processing time for storing data in the track buffer memory by the transfer control section.

Note that the length of the basic part of a realistic repeating pattern is 20
Since the length of data for one track is about 40,000 bytes, the storage processing time can be reduced to 0.05%.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data transfer unit of a disk control device according to an embodiment of the present invention, FIG. 2 is a timing diagram of a normal write operation in FIG. 1, and FIG. FIG. 4 is a timing diagram of an operation in which a continuous repeating pattern of data is transferred to a disk device by the control device itself. 1... Transfer control unit, 2.3 and 5... Address pointer, 4... Address comparison circuit, 6.7 and 9... Selection circuit, 8 and 11... Data register, 12 and 13 ...Register, 10...Track buffer memory, 21-27...Data line, 31-33...Selection line,
41 to 48... Control lines, 51 to 54... Address lines, 61 and 62... Control lines from higher or lower levels, 7
1 to 73: Data line between upper or lower.

Claims (1)

[Claims] 1. In a storage control device that has a buffer memory, an address pointer that supplies its address, and a data transfer control unit, and performs data transfer between a CPU and an external storage device,
A storage control device comprising: an address comparison section that compares the value of the address pointer with an arbitrary value given in advance; and means for setting an arbitrary value in the address pointer based on the comparison result of the address comparison section.