JPH0248910B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to aligning gate lines of an active matrix panel driving integrated circuit (hereinafter referred to as active matrix substrate).

FIG. 1 shows a schematic diagram of an element section consisting of individual switching transistors and data holding capacitors arranged in a matrix on an active matrix substrate. The area surrounded by dotted line 3 in the figure is the element part, and the switching transistor 4
, a data holding capacitor 5 , a liquid crystal driving electrode, and a liquid crystal 6 are arranged in a matrix shape repeatedly in the horizontal and vertical directions. The basic operation is to control ON/OFF of the switching transistor by the signal on gate line 1.
When the transistor turns on, source line 2
The voltage is charged to the data retention capacitor connected to the drain via the channel section,
When it is OFF, the charge stored in the capacitor is
It is held for a period of time until the next transistor turns on.

FIG. 2 shows a conventional pattern formed on a Si substrate to realize the element portion shown in FIG. 1. In the figure, 1 is a gate line made of polycrystalline silicon, and 2 is a source line made of Al. 3
4 is a switching transistor, and 4 is a data holding capacitor. Each switching transistor is located at the intersection of the gate line and the source line, and the drain is connected by Al to a capacitor made of polycrystalline silicon, a Si substrate, and a thin Si oxide film. In an actual active matrix substrate, this pattern is repeatedly patterned at least 200 times in the horizontal and vertical directions.
Therefore, if leakage occurs at even one location in the gate line, source line, or element portion, it will result in a line defect and an element defect, and such an active matrix substrate will be considered defective. However, due to yield issues, it is possible to repair defective chips by cutting out the defective parts of the defective chip and repairing it to a non-defective chip. It forms a contact with the source and a gate. According to data from actual chip measurements,
Regarding the source line, it is necessary to make a hole in the field oxide film to connect to the source diffusion region of each element, so defects that cause leakage are likely to occur around the contact hole. The benefits of branching out can be said to be great. However, since the gate line is formed on the field oxide film and also in the channel portion through the gate oxide film, the rate of occurrence of defects causing leakage is sufficiently lower than that of the source line. As a result, it can be said that there is almost no merit in branching from the main line to the channel section. On the contrary, the disadvantage is that defects are more likely to occur because the area of polycrystalline silicon forming the gate line is large. Furthermore, the polycrystalline silicon photo-etch process has extremely low compatibility with that of existing Si gate integrated circuits, and if a 3 to 4 cm piece of 10 μm polycrystalline silicon is formed using the gate line pattern shown in Figure 2, However, there is a drawback that the photoresist formed for etching the polycrystalline silicon pattern branching from the main line to the channel section may peel off, and pattern defects in the polycrystalline silicon are likely to occur. If we aim to improve chip yield using existing Si gate technology, it is desirable to improve the gate line pattern. Furthermore, in conventional gate line patterns, it is necessary to provide an interval of several μm to 10-odd μm between the gate polycrystalline silicon in the channel part and the polycrystalline silicon forming the data retention capacitor in order to insulate them. The disadvantage is that the capacitance of the capacitor cannot be increased. Since the liquid crystal is driven by the charge stored in the capacitor, it is necessary to hold the charge in the capacitor for the time from when the switching transistor is turned on for the first time until it is turned on again. but,
Polycrystalline silicon, which is one electrode of the capacitor, and
Considering leakage between Si substrates and leakage due to train displacement, the capacitance of conventional capacitors has little margin, and the voltage drops during the charge hold time, making it difficult to drive the liquid crystal stably. Ta.

The present invention eliminates such drawbacks, and its objectives are, firstly, to reduce defects occurring in gate lines, and secondly, to increase the capacitance of data retention capacitors without changing the size of the element section. It is to let. The present invention will be described in detail below based on Examples.

FIG. 3 shows an embodiment according to the present invention. The numbers in the figure are the same as in FIG. 2, and are omitted here. In this embodiment, the gate line is straightened to form a pattern in which the channel portion of the switching transistor is directly below the gate line. Since the area of the gate line is reduced compared to the conventional method, the defect rate is reduced to 2/3 to 1/2 of the conventional method. Although the defect occurrence rate of gate lines is basically low, this embodiment can bring it even closer to zero defects. Furthermore, since it is a simple polycrystalline silicon line, patterning can be easily performed using existing Si gate technology. Furthermore, since there is no branching of the gate channel portion caused by polycrystalline silicon, the area of polycrystalline silicon forming the capacitor can be increased. As is clear from the figure, the area increases by about 30%, so it easily increases by about 30% in proportion to the area.

With the above configuration, the following effects can be obtained.

That is, (a) By making the gate line straight without branching, the area of the gate line is reduced and patterning is simple and easy, so defects occurring in the gate line can be significantly reduced. .

(b) Since the area of the data holding capacitor can be increased without changing the area of the switching element, the display area can be increased and the aperture ratio can be significantly improved.

(c) Since wiring resistance and wiring capacitance can be reduced,
The entire screen of the display device can be made larger.

(d) Since the wiring area is reduced, there is no need to apply unnecessary DC electric fields to the liquid crystal, improving reliability and extending the life of the liquid crystal.

(e) Since the capacitance of the data storage capacitor can be increased, it is possible to drive the liquid crystal even when considering drain junction leakage and charge discharge due to leakage between the polycrystalline silicon and the substrate. It is possible to hold sufficient charge, and an active matrix liquid crystal device with a large capacity margin can be realized.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an element section consisting of a switching transistor and a capacitor. FIG. 2 shows a pattern of a conventional element section. FIG. 3 is a pattern of an element portion according to the present invention.

Claims (1)

[Claims] 1 A liquid crystal is sealed in a pair of substrates, and on one of the substrates are pixel electrodes arranged in a matrix, transistors connected to the pixel electrodes, and data signals supplied to the source electrodes of the transistors. In a liquid crystal display device having a plurality of pixel units each including a data line formed by a data line formed by a transistor, and a gate line formed by a gate line formed by supplying a gate signal to a gate electrode of the transistor, a channel region extends in the line width direction of the first gate line. a first transistor formed to intersect with the gate line of the first pixel unit and to span the first pixel unit and the second pixel unit;
The pixel electrode located in the first pixel unit is connected to the drain located in the first pixel unit of the transistor, and the channel region is connected to the second gate in the line width direction of the second gate line. the second pixel unit and the third pixel unit.
a second transistor formed across a pixel unit; a source electrode of the second transistor connected to the data line and located in the second pixel unit;
A liquid crystal display device comprising: the pixel electrode located in the second pixel unit connected to the drain located in the second pixel unit of the second transistor.