JPS603702B2 - conductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a memory array in a semiconductor memory.

Conventionally, memories that consist of one bit with one transistor, such as MOS (Mene1-Oxide-Semic-o
The circuits shown in Figures 1 and 2 were used in memory.

That is, in FIG. 1, when reading out a memory cell MCo, for example, a word line Wo and another data line Do are connected.
A pulse is simultaneously applied to the dummy word line DW, which belongs to the memory cells MCo and DM, and the minute differential signal output appearing on the two data lines Do, Do is used as the read signal from the memory cells MCo and DM, to the set signal Set of the preamplifier PAo. By turning on the preamplifier PAo, the preamplifier PAo is operated and amplified, and the voltage appearing on one of the data lines Do and Do is detected to discriminate between information "1" and "0". The reason why differential signal output is generated here is as follows. Since the voltage stored in the capacitor Co of the dummy cell DM is set to approximately the middle of the voltages corresponding to the information "1" and "0" stored in the memory cell Co, data cannot be read from the dummy cell. The voltage appearing on the line is approximately midway between the data line voltage due to the "1" and "0" output of the memory cell. Therefore, the difference between this intermediate value and the "1" and "0" outputs becomes a differential signal output with different polarity.

Figure 2 shows a plurality of circuits shown in Figure 1 (for example, 6 here).
4) is a diagram schematically showing a circuit in consideration of the geometrical arrangement when mounted in one chip to constitute one memory.

In the figure, the white circles are memory cells, and the black circles are dummy cells.
For example, in order to take out the signal appearing on the data line Do as described above, the signal on the data line Do, which turns on the transistor Qo according to the address signal, is input to the main amplifier MA and amplified, and the data output Dout and take it out of the chip. Now, the drawbacks of such a configuration can be summarized as follows. In other words, ■Data lines Do, Do
Only one of the differential signals appearing in the main amplifier MA
Since it is amplified by , it is inferior in terms of high speed. ■ In order to extract one signal, electrical imbalance between Do and Do tends to occur, causing malfunction. ■ Data lines Do and D must have their electrical characteristics balanced.

are not geometrically close within the chip, so Do,
Unbalanced noise easily couples to Do. This may cause malfunction if the preamplifier is turned on. Due to these drawbacks, there has been a limit to the design of high-speed and highly stable LSI memories. One object of the present invention is to provide a semiconductor memory with a large noise margin.An object of the present invention is to provide a semiconductor memory that allows highly integrated cell packing.

To this end, one embodiment of the present invention provides a memory cell layout of a dynamic random access memory, in which a voltage is placed on the channel of the access transistor of each cell and in the center of the capacitor coupled thereto, and By arranging the data lines parallel to the channel length direction, a highly integrated and low noise cell is achieved.

This will be explained in detail in the examples above. FIG. 3 shows the circuit.

That is, the data line pair Do, where differential read signals appear,
D. are arranged close to each other in parallel as shown in the figure, and one each of the word lines (Wo to W63, DWo, DW,) and Do
, Do, a memory cell is connected to only one of the intersections. When reading a certain memory cell (for example, MC63), the data line (Do
) are simultaneously read out, and the differential voltage appearing on the data lines Do, Do is effectively used by the preamplifier P. Further, the differential signal amplified by the preamplifier P passes through transistors Qo and Qo by application of the address signal Ao, which is the output of the decoder, and is input to the differential amplifier MA, where it is differentially amplified again. In this way, in the present invention, <Do, Do
The electrical balance of is not disturbed in any way. FIG. 4 is a schematic diagram of a method of connecting memory cells (8 bits) while maintaining electrical balance between Do and Do. In the figure a,
b, c are Do, Do every 1, every 2, 4
In this method, memory cells are connected every other place. Figure 5a,
Figure 6 shows Figures 4b and 4c using a silicon gate process.
This is an example of a layout that achieves this. FIG. 5b is a cross-sectional view of section AA' in FIG. 5a.

In the figure, storage capacitor forming electrode c formed with policy J
p is for forming a storage capacitor Co in the memory cell as shown in FIG. 400, 41 are formed in the Kawama silicon substrate 600 and are a drain and source (or source and drain) for forming a transistor Q, and 420 is a drain (or source) for forming Co corresponding to 410. be.

The storage capacitor forming electrode Cp and the word lines W59, etc. are formed of polysilicon, and the data lines D, etc. are formed of aluminum.

The data line D, etc. and the word line W59, etc. are separated by an insulating film 200. Reference numeral 100 indicates a contact portion between the data lines Do, Do, etc. and the diffusion layer 400.

In N-channel MOS, the storage capacitance Co is formed by c
When a high voltage is applied to p, the capacitance between cp and the channel formed directly below becomes Co.

To explain the operation using FIG. 5, the word line, for example, W
6. When a pulse voltage is applied to the transistor Q (corresponding to Q in MCo in Figure 1), it turns on, and the memory voltage of Co is divided by the capacitance of the data line Do and Co, and a voltage appears on Do. . On the other hand, since the transistor Q does not exist on the data line Do paired with this, no output appears. The output appearing at Do is only the output from the dummy cell (not shown), as described above. Furthermore, the fifth
As is clear from the figure, Do and D. Because the AI wiring exists in the middle of the distance between the diffusion layers of the contact part,
You can make it big. Therefore, there is an advantage that punch-through between Do and D can be avoided. Another advantage of FIG. 3 is that the layout of the preamplifier PAo is easier than in the past. In other words, in the conventional Figures 1 and 2, there is a "
It is necessary to lay out a circuit board that occupies a much larger area than a memory cell and has a complicated circuit configuration, which is extremely difficult considering the pitch of the data lines. However, in Fig. 3, there is approximately twice as much space in the layout as in the conventional layout in the data line pitch direction, so
Layout becomes extremely easy. Also preamplifier PA
o may be placed on the MA side as shown in FIG. 3, or on the pond edge (W63 side) above Do, Do.

By arranging P on the W63 side, control circuits that are relatively difficult to layout (P, Qo, etc.) will not be concentrated at one end, as shown in FIG. Depending on the case, the pre-aps may be arranged alternately on the MA side and the W63 side on the data line. As described above, according to the present invention, the degree of freedom in layout can be greatly increased. Furthermore, in FIGS. 5 and 6, the word line is made of poly-Si, but the word line is made of A
A similar layout is possible in the case of I, and the same applies to the case of AI gates.

Also, in this example, one bit is configured with one transistor, but in order to extract signals differentially from the data pair lines, a memory cell is connected only to one of the two intersections with the word line. It is clear that the concept shown in FIGS. 3 and 4 using dummy cells can be applied to all memory LSIs.

In FIG. 3, CD and CD are common data lines for data writing and logical output. From the above, it is possible to realize a memory BI with high speed and highly stable operation.

[Brief Description of the Drawings] Figures 1 and 2 show the structure of a secondary memory in which one bit is configured with one transistor; Example, Fig. 4 shows a memory cell connection method, and Figs. 5 and 6 show an example of a layout using a Si gate as an example. Do, Do, D,: data line, Wo, W62: word line , DWo, DW, ; Word line of dummy cell, MC. , MC, : Memory cell, DMo, DM, : Dummy cell,
C. :Storage capacity, transistor in Q memory cell, WD:
Word driver, Q〇,Q. ~Q3: Data line selection transistor, to ~A63: Address signal, PAo~PA
63: Preamplifier, MA: Main amplifier, Set: Set signal CP: Electrode for Co formation. Fig. 2 Fig. 1 Fig. 3 Fig. 4 Fig. 5 Fig. 6

Claims (1)

[Claims] 1. A plurality of memory cells each having a FET are arranged in a matrix,
In a semiconductor memory in which a word line for flowing a signal to control the switching operation of the FET runs in the row direction, and a data line for reading a storage signal from the FET runs in the column direction, the channel direction between the source and drain of the FET is is the column direction, the channel and the data line are formed to overlap when viewed from a plane, and the data lines are extended parallel to each other, and one set of adjacent data lines is coupled to a differential sense amplifier. A semiconductor memory characterized by