JPH0249056B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a master-slave flip-flop with reduced power consumption.

Although the degree of integration has improved with advances in semiconductor technology, the problem of heat generation has arisen. in general
The CMOS type consumes less power, so there are relatively few problems with heat generation, but there are problems when increasing the degree of integration. Furthermore, in the nMOS type, pMOS type, or bipolar type, the problem of heat generation increases as the degree of integration increases. Although various configurations of flip-flops are known, the conventional master-slave flip-flop has generally had the configuration shown in FIG.
CL is a clock terminal, IN is an input terminal,
Q, is an output terminal.

FIG. 2 is an explanatory diagram of the operation of FIG. 1. Assuming that the clock a is shown in FIG. 2 a and the input signal b is shown in FIG. 2 b, the output signal c of the inverter INV2 is as shown in FIG. 2 c. So, Nand Gate G1,G
The output signals d and e of 2 are as shown in FIG. 2 d and e. Therefore, the output signals f and g of the NAND gates G3 and G4 constituting the latch circuit on the master side become as shown in FIG. 2 f and g when the output signal e of the NAND gate G2 is inverted. Also, clock a is inverted by inverter INV1 and connected to NAND gate G5,
Since the output signals h and i of the NAND gates G7 and G8 constituting the latch circuit on the slave side are applied to the latch circuit G6, the output signals h and i of FIG.
Invert as shown.

For example, a NAND gate is composed of transistors Q1 to Q3 as shown in FIG. 3, and when both input signals A and B are "1", transistors Q2 and Q
3 is turned on, and the output signal C becomes "0". That is, when the output signal C is "0", current flows through the transistors Q2 and Q3 due to the power supply voltage _VD . Therefore, in the aforementioned NAND gates G1 to G8, current flows and heat is generated when the output signal is "0".

In the master-slave flip-flop as described above, the slave side holds information, but the master side transfers the read information to the slave side. The purpose of this is to reduce power consumption by controlling so that no current flows through the gate on the master side except during operation. Examples will be described in detail below.

FIG. 4 shows an embodiment of the present invention, in which G11 to G1
9 is a NAND gate, INV is an inverter, CL is a clock terminal, IN is an input terminal, ST is a strobe terminal, and Q is an output terminal. Fig. 5 is an explanatory diagram of the operation. If the clock a applied to the clock terminal CL is shown in Fig. 5, and the input signal b applied to the input terminal IN is shown in Fig. 5, then the strobe applied to the strobe terminal ST is as shown in Fig. 5. The signal c has a pulse width including the period in which the clock a is "0" and the period immediately before the period, as shown in FIG. That is, the pulse width includes a period in which the latch circuit on the slave side performs a read operation using a signal obtained by inverting clock a, and the shortest period immediately before this period during which the latch circuit on the master side can read input signal b. That is.

The output signal d of the NAND gate G19 becomes the NAND logic output of the strobe signal c and the input signal b,
The result is as shown in FIG. 5d. Therefore, the output signals e and f of the NAND gates G11 and G12 are always "1", the strobe signal c is "1", and the clock a is "1".
When the input signal b is "1", the output signal e is "0", and when the input signal b is "0", the output signal f is "0". That is, as shown in FIG. 5e and f, it becomes "0" for only a short period.

Furthermore, the output signals g and h of the NAND gates G13 and G14 that constitute the latch circuit on the master side become "0" according to the output signals e and f only during the period when the strobe signal c is "1", and otherwise become "1". ” becomes.
That is, the results are as shown in FIG. 5g and h.

Inverter is installed in NAND gates G15 and G16.
Since the clock a inverted by INV and the output signals g and h of the NAND gates G13 and G14 are added, the output signals i and j of the NAND gates G17 and G18 which constitute the latch circuit on the slave side depend on the timing of the clock a. Input signal b is held and becomes as shown in FIG. 5i and j.

In the conventional example shown in FIG. 1 and the embodiment of the present invention shown in FIG. 4, if the input signal b and the clock a are the same, the output signals are the same, but the output signals d ~g corresponds to "1" and "0" of the input signal b, and becomes "0" only during the period when the strobe signal c is "1", so
Constant power consumption will be significantly reduced.

As explained above, the present invention includes a latch circuit consisting of a plurality of gate circuits such as NAND gates on the master side which are read and latched by the clock a;
It has a latch circuit consisting of a plurality of gate circuits such as NAND gates on the slave side which reads and latches the output signal of the latch circuit on the master side using a signal obtained by inverting the clock a by an inverter INV. When the strobe signal c is input, the output logic level of each gate circuit constituting the circuit becomes the logic level according to the input logic level, and when the strobe signal c is not input, It has a configuration that is fixed to a logic level that results in low power consumption, such as a logic level of "1", and the strobe signal c is set to the shortest period during which the latch circuit on the master side can read the input signal b. , has a pulse width that includes a period during which the latch circuit on the slave side performs a reading operation, and the latch circuit on the slave side is always in an operating state, but the latch circuit on the master side reads input signal b. Since it is in an operating state only during this period and is in a low power consumption state during other periods, the power consumption on the master side, which accounts for about half of the configuration of a master-slave flip-flop, can be significantly reduced.

Therefore, by simply adding a few elements for applying the strobe signal c, the overall amount of heat generated can be suppressed, which has the advantage of facilitating high integration. Note that the present invention is not limited to the above-described embodiments, and other theoretical gates such as the NAND gate may be used.

[Brief explanation of drawings]

FIG. 1 is a conventional master-slave flip-flop, FIG. 2 is an explanatory diagram of the operation of FIG. 1, FIG. 3 is a circuit diagram of an example of a NAND circuit, and FIG. 4 is a master-slave flip-flop according to an embodiment of the present invention. FIG. 5 is an explanatory diagram of the operation of FIG. 4. G11 to G19 are NAND circuits, INV is an inverter, IN is an input terminal, CL is a clock terminal, ST
is a strobe terminal, and Q is an output terminal.

Claims (1)

[Claims] 1. A latch circuit consisting of a plurality of gate circuits on the master side that reads and latches an input signal by a lock, and an output signal of the latch circuit on the master side using a signal obtained by inverting the clock. In a master-slave flip-flop having a latch circuit consisting of a plurality of gate circuits on the slave side that reads and latches, each gate circuit constituting the latch circuit on the master side has an output logic level equal to that of the strobe signal. When the strobe signal is input, the logic level becomes a logic level according to the input logic level, and when the strobe signal is not input, it is fixed at a specific logic level that reduces power consumption, and the strobe signal is
The pulse width is characterized by having a pulse width including a period in which the latch circuit on the slave side performs a read operation and a shortest period immediately before the period during which the latch circuit on the master side can read the input signal. Master-slave flip-flop.