JPH0249734Y2 - - Google Patents

Description

[Detailed explanation of the idea]

<Industrial Application Field> The present invention relates to a buried gate static induction transistor in which the space between two gate electrodes is divided and semiconductor materials with different impurities are embedded in each of the gate electrodes. <Conventional technology> Static induction transistors (hereinafter abbreviated as SIT) have two types: a buried gate type suitable for high power and high voltage applications, and a gate and source type suitable for low power and high speed applications. and surface wiring type, which are formed on almost the same plane. As shown in the plan view of the structural outline in Figure 2, the conventional buried gate SIT generally uses a group of intrinsic semiconductors such as silicon Si and germanium Ge, as well as boron B,
Group group elements such as aluminum Al and gallium Ga are diffused as acceptors, and gate electrode metals 6 and 6' are provided at both ends of the gate peripheral portion 7 as power feeding points. A drain is placed within this gate peripheral portion 7.
A SIT is formed by embedding a first buried gate 4 made of a buried gate P ⁺ layer 2 between the N ⁻ and source N layers 3 . <Problems to be solved by the invention> In the conventional buried gate type SIT, due to the relatively large gate resistance of the first buried gate 4, the portion away from the gate electrode metal 6, 6' which is the power supply point In this case, the response of the gate is delayed compared to the nearby part, so
It was difficult to use it at frequencies exceeding 1MHz. <Means for solving the problem> A buried gate provided perpendicularly to the direction connecting the source N layer 3 and the drain N ⁻ 1 is provided at both ends of the gate peripheral portion 7 surrounding the buried gate P ⁺ layer 2. electrode 6,
In a buried gate static induction transistor with 6' as the power supply point, the impurity density of the second buried gate is lower than that of the first buried gate near the gate electrodes 6 and 6' of the buried gate P ⁺ layer 2. It is a static induction type transistor with a large size. <Operation> By increasing the impurity density in the central part of the buried gate, the value of gate resistance is reduced, and the operating frequency is increased. <Example> An example of the buried gate static induction transistor of the present invention will be described with reference to the drawings. As shown in Figure 1, a buried gate is buried between the source N layer 3 and the drain N ^- layer 1 on the upper surface.
Gate periphery 7 with P ⁺ layer 2 provided on its periphery
between the gate electrode metals 6 and 6' provided as a power supply point at both ends of the first buried gate 4 near the power supply point.
The second buried gate 5 is formed by dividing into a region and a second buried gate 5 region located far away in the middle. These divided first embedded gates 4
The impurity density in the second buried gate 5 region is made higher than the impurity density in the second buried gate 5 region. The impurity density here refers to the ratio of the number of atoms per 1 cm ³ when a group element B is mixed as an impurity to the intrinsic semiconductor Si, as is practically used. As a specific example, for a length of the first buried gate 4 of 3 mm and a length of the second buried gate 5 of 4 mm, the impurity density of the drain N ^-layer 1 is N _D =5×10 ¹³ cm ^-3 , and the source N The impurity density of layer 3 is N _d =1×10 ¹⁵ cm ⁻³ .
On the other hand, the density of the first buried gate 4 and the density of the second buried gate 5 are different from that of the conventional example and the sample 6 according to the present invention.
The respective data and voltage amplification factor μ for each
Table 1 shows the comparatively measured values of the frequency f _T (MHz) that decreases by 3 dB.

[Table] As is clear from Table 1, the density of the first buried gate 4 is N _s1 = 2 or 3×10 ^-19 cm ^-3 , and the density of the second buried gate 5 is N _s2 = 2 to 6×10 ^- N _s2 at ¹⁹ cm ^-3
By increasing , the frequency used can be greatly improved. However, currently f _T required for 1kW SIT
The value that can be produced is about 1.2MHz. Here, as a method of obtaining gates with different impurity densities, selective diffusion is performed separately on the first buried gate 4 and the second buried gate 5, or pre-deposition is first performed on all gate patterns under conditions of high impurity density. Thereafter, a portion of the boron glass formed by pre-deposition is removed only in the first buried gate 4 area, and then the entire area is heated at a high temperature, ie, a so-called drive-in process is performed. In this embodiment, the impurity density ratio between the first buried gate 4 and the second buried gate 5 is 1:3, but it can be changed by adjusting the amount of boron glass removed from the first buried gate 4. Furthermore, this ratio can be varied. <Effects of the invention> As stated above, according to the invention, the allowable loss
In a SIT of about 1kW, the frequency dependence of the voltage amplification factor μ is 2.0MHz when it decreases by 3dB, compared to the conventional 0.8MHz.
It is significantly improved compared to . Therefore, it is possible to improve the frequency characteristics without changing the price, shape, or power value of the element.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the static induction transistor of the present invention, in which a is an external plan view, b is a vertical front view taken along line A-A in a, c is a vertical side view taken along line B-B in a, and FIG. The figure is an external plan view of a conventional static induction transistor. Note that 1...Drain N ^- layer, 2...Buried gate P ⁺ layer, 3...Source N layer, 4...First buried gate, 5...Second buried gate, 6, 6'... ...Gate electrode metal, 7...Gate periphery.

Claims (1)

[Scope of utility model registration request] Source N layer 3 on the top surface and drain N ^- layer 1 on the bottom surface
A buried gate static induction type transistor in which gate electrodes 6 and 6' are provided as power feeding points at both ends of a gate peripheral area 7 surrounding a buried gate P ⁺ layer 2 provided perpendicular to the direction connecting between In the electrostatic induction type transistor, the impurity density is higher in the buried gate P ⁺ layer 2 between the gate electrodes 6 and 6' at a distance from both electrodes than near the electrodes.