JPH0250623B2 - - Google Patents

Info

Publication number
JPH0250623B2
JPH0250623B2 JP57052629A JP5262982A JPH0250623B2 JP H0250623 B2 JPH0250623 B2 JP H0250623B2 JP 57052629 A JP57052629 A JP 57052629A JP 5262982 A JP5262982 A JP 5262982A JP H0250623 B2 JPH0250623 B2 JP H0250623B2
Authority
JP
Japan
Prior art keywords
lead
terminal
chip
power supply
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57052629A
Other languages
Japanese (ja)
Other versions
JPS58169949A (en
Inventor
Masahiro Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP57052629A priority Critical patent/JPS58169949A/en
Publication of JPS58169949A publication Critical patent/JPS58169949A/en
Publication of JPH0250623B2 publication Critical patent/JPH0250623B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は正電源端子、負電源端子（又はグラン
ド端子）および入出力端子等の複数端子を有する
半導体チツプを装着し、同チツプ内の上記各端子
が外部リード端子に結線されるインナーリード部
を有する半導体装置に関するものである。Detailed Description of the Invention The present invention includes a semiconductor chip having multiple terminals such as a positive power terminal, a negative power terminal (or ground terminal), and an input/output terminal, and each of the above terminals in the chip is connected to an external lead terminal. The present invention relates to a semiconductor device having an inner lead portion to which wires are connected.

従来の（2n＋１）ピンシングルインライン型
半導体装置の端子結合部を第１図に示す。ここで
ｎはｎ１の正の整数である。通常シングルイン
ライン型半導体装置に使用されるリード構体は、
中央のインナーリードをダイパツドに繋がるハン
ガーの役割を兼ねており、回路の最低電位にとる
ことが多い。ここで、チツプ上の１，２，…２ｎ
は端子番号、１′，２′，…（２ｎ＋１）′はリー
ド番号を表わし、W1，W2…W2o+1は端子とリー
ドを結線するワイヤーを表わす。また、１０１は
ダイパツド、１０２はチツプを表わす記号であ
る。以下、第１図に示すように、正電源、負電源
ならびに一対の入出力端子で構成される偶数個の
信号処理回路を並列的に有する半導体チツプに対
するワイヤリングについてのべる。この場合、端
子の構成は正電源を端子１に負電源を端子ｎ＋１
に配置し、信号処理回路の一対の入出力端子は前
記端子１と同ｎ＋１の位置を結ぶ直線に関して対
称となるように配置（第１図では端子ｎ，ｎ＋
１，ｎ＋２）すれば特性が揃つた信号処理回路が
得られる。このチツプを第１図に示すごとくワイ
ヤリングを行なうとリード（ｎ＋１）′に対して
正電源用リードおよび入出力用リードが対称に配
置され、シングルインライン型パツケージから方
向性を完全に取除くことができシングルインライ
ン型パツケージの特長を生かした半導体集積回路
が得られる。しかし、従来の構成では次のような
問題がある。 FIG. 1 shows a terminal coupling portion of a conventional (2n+1) pin single in-line semiconductor device. Here, n is a positive integer of n1. The lead structure normally used for single in-line semiconductor devices is
It also serves as a hanger that connects the central inner lead to the die pad, and is often set to the lowest potential of the circuit. Here, 1, 2,...2n on the chip
are terminal numbers, 1', 2', ... (2n+1)' are lead numbers, and W 1 , W 2 ... W 2o+1 are wires connecting the terminals and leads. Further, 101 is a symbol representing a die pad, and 102 is a symbol representing a chip. Hereinafter, as shown in FIG. 1, wiring for a semiconductor chip having an even number of signal processing circuits in parallel, each consisting of a positive power source, a negative power source, and a pair of input/output terminals, will be described. In this case, the terminal configuration is positive power supply at terminal 1 and negative power supply at terminal n+1.
and the pair of input/output terminals of the signal processing circuit are arranged symmetrically with respect to the straight line connecting the terminal 1 and the n+1 position (in Fig. 1, the input/output terminals of the signal processing circuit are
1, n+2), a signal processing circuit with uniform characteristics can be obtained. When this chip is wired as shown in Figure 1, the positive power supply lead and input/output leads are placed symmetrically with respect to lead (n+1)', making it possible to completely eliminate directivity from a single in-line package. A semiconductor integrated circuit that takes advantage of the features of a single in-line package can be obtained. However, the conventional configuration has the following problems.

(1) 正電源端子に２本のワイヤーが必要（第１図
でW1，W2o+1） (2) 正電源端子１がチツプ１０１中央端に位置す
るためワイヤーが長くなり、ワイヤーだれ等の
問題が発生する場合がある。(1) Two wires are required for the positive power supply terminal (W 1 , W 2o+1 in Figure 1) (2) Since the positive power supply terminal 1 is located at the center end of the chip 101, the wire is long and the wire may sag. problems may occur.

(3) ２の問題を除去しようとすれば、チツプの正
電源端子が２個必要となり、チツプ面積が増加
する。(3) If problem 2 is to be eliminated, two positive power supply terminals for the chip are required, which increases the chip area.

(4) リード１′およびリード（２ｎ＋１）′をプリ
ント回路基板のジヤンパーとして利用する場
合、ワイヤー、内部アルミ配線を用いるため電
流容量を大きくとることができない。(4) When lead 1' and lead (2n+1)' are used as a jumper for a printed circuit board, a large current capacity cannot be achieved because wires and internal aluminum wiring are used.

(5) 負電源のジヤンパーは構造上不可能である。(5) Jumper of negative power supply is structurally impossible.

本発明は、対称配置の特長はそのまま生かしな
がら上記５点の問題を完全に取除くことができる
半導体装置を提供せんとするものである。 The present invention aims to provide a semiconductor device that can completely eliminate the five problems mentioned above while still taking advantage of the advantages of symmetrical arrangement.

本発明に基づく（2n＋１）ピンシングルイン
ライン型半導体装置のリード結線部を第２図、第
３図に示す。第２図はリード１′およびリード
（２ｎ＋１）′を正電源ジヤンパーとして用いるこ
とができるように一体にしたものである。また、
第３図ではリード１′およびリード（２ｎ＋
１）′を負電源ジヤンパーとして用いることがで
きるようにしたものである。すなわち、第２図の
実施例はリード１′，（２ｎ＋１）′を共通にし、
同図の様に共通リードを電源端子１の近傍に設
け、この共通リードと電源端子１とをワイヤー
W1により接続した場合を示し、第３図の実施例
はリード１′，（２ｎ＋１）′を共通にするととも
にチツプ１０２下にも及ぶ様にしたもので、共通
リードを負電源ジヤンパーとして用いることを可
能とした場合を示す。尚、第２図、第３図で第１
図と同一番号は同一部分を示す。どちらの場合で
も端子１からリード１′へと最短距離でワイヤリ
ングされる。この構造によれば従来２本必要とし
た正電源用あるいは負電源用のワイヤーも１本で
よい。また、リード自身をジヤンパーとして利用
するため電流容量も大きくとることができる。 The lead connection portion of the (2n+1) pin single in-line type semiconductor device based on the present invention is shown in FIGS. 2 and 3. In FIG. 2, lead 1' and lead (2n+1)' are integrated so that they can be used as a positive power jumper. Also,
In Figure 3, lead 1' and lead (2n+
1)' can be used as a negative power supply jumper. That is, in the embodiment of FIG. 2, the leads 1' and (2n+1)' are common,
As shown in the figure, a common lead is provided near power terminal 1, and this common lead and power terminal 1 are connected by wire.
In the embodiment shown in FIG . 3, leads 1' and (2n+1)' are made common and extend below the chip 102, and the common lead can be used as a negative power jumper. Indicates the case where this is possible. In addition, in Figures 2 and 3,
The same numbers as in the figure indicate the same parts. In either case, wiring is performed from terminal 1 to lead 1' over the shortest distance. According to this structure, only one wire is required for the positive power source or the negative power source, whereas conventionally two wires are required. Furthermore, since the lead itself is used as a jumper, a large current capacity can be achieved.

次に、本発明の具体的実施例として９ピンシン
グルインライン型パツケージに組込んだデユアル
オペアンプを第４図に示す。第４図ａはワイヤリ
ング図であり、第４図ｂはパツケージ外形図であ
る。ここで、１０３はチツプの方向を示す部分
で、１０４は品名を表わす部分であり、同図にお
いて第２図、第３図と同一番号は同一部分を示
す。 Next, FIG. 4 shows a dual operational amplifier built into a 9-pin single in-line package as a specific embodiment of the present invention. FIG. 4a is a wiring diagram, and FIG. 4b is a package outline diagram. Here, 103 is a part showing the direction of the chip, and 104 is a part showing the product name. In this figure, the same numbers as in FIGS. 2 and 3 indicate the same parts.

従来、正電源、負電源端子および入出力端子を
対称的に配した偶数個の信号処理回路を有する半
導体チツプを（2n＋１）ピンシングルインライ
ン型パツケージにパツケージングする際、第１図
のように、リード（ｎ＋１）′に関し、対称配置
を行なえば半導体集積回路から方向性を除去する
ことができ、リード１′および（２ｎ＋１）′をジ
ヤンパーとして利用できる特長があつた。 Conventionally, when packaging a semiconductor chip having an even number of signal processing circuits with positive power supply terminals, negative power supply terminals, and input/output terminals arranged symmetrically into a (2n+1) pin single in-line package, as shown in Figure 1, Regarding the leads (n+1)', if the leads are arranged symmetrically, the directivity can be removed from the semiconductor integrated circuit, and the leads 1' and (2n+1)' can be used as jumpers.

本発明は第２図ないし第４図に示すリード構成
によつて上記特長はそのままで、さらに以下にの
べる効果をもつものである。 The present invention maintains the above-mentioned features by using the lead configurations shown in FIGS. 2 to 4, and also has the following effects.

(1) 従来対称性を保つため２本必要としたワイヤ
ーを最小の長さで１本にすることができる。さ
らにパツドも１個でよいからチツプサイズを径
大化することがない。(1) The wire that previously required two wires to maintain symmetry can be reduced to one wire with the minimum length. Furthermore, since only one pad is required, there is no need to increase the chip size.

(2) リード形状を選択的に設計すれば、負電源を
ジヤンパーとして利用することもできる。(2) By selectively designing the lead shape, the negative power supply can be used as a jumper.

(3) 従来はワイヤーをジヤンパーとしており、従
つて電流容量に制限があつたが、リードをジヤ
ンパーとしているため電流容量を大きくとれ、
しかも内部回路への影響が皆無である。(3) Previously, wires were used as jumpers, which limited the current capacity, but since the leads were used as jumpers, the current capacity could be increased.
Furthermore, there is no effect on the internal circuitry.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の（2n＋１）ピンシングルイン
ライン型半導体装置のチツプ端子とインナーリー
ドの結線図、第２図、第３図は本発明の実施例に
係る半導体装置の端子部結線図、第４図ａ，ｂは
本発明の別の具体的事例における端子部結線図な
らびにパツケージに組込んだ外形図である。 １，２，〜２ｎ……チツプ内回路端子、１′，
２〜（２ｎ＋１）′……リード、W1〜W2o……ワ
イヤー、１０１……ダイパツド、１０２……半導
体チツプ。 FIG. 1 is a wiring diagram of a chip terminal and an inner lead of a conventional (2n+1) pin single in-line semiconductor device, FIGS. 2 and 3 are terminal wiring diagrams of a semiconductor device according to an embodiment of the present invention, and FIG. Figures a and b are a terminal connection diagram and an external view of the terminal part assembled into a package in another specific example of the present invention. 1, 2, ~2n...Chip internal circuit terminals, 1',
2 to (2n+1)'...Lead, W1 to W2o ...Wire, 101...Die pad, 102...Semiconductor chip.

Claims (1)

【特許請求の範囲】[Claims] １ 2n個（ｎ：ｎ１の整数）の端子を有する
半導体チツプと、前記各端子に接続される2n＋
１個のアウターリードとを有し、前記アウターリ
ードの２個以上がインナーリード部において一体
化接続されていることを特徴とする半導体装置。1 A semiconductor chip having 2n terminals (n: an integer of n1), and a 2n+ semiconductor chip connected to each of the terminals.
1. A semiconductor device comprising one outer lead, and two or more of the outer leads are integrally connected at an inner lead portion.
JP57052629A 1982-03-30 1982-03-30 Semiconductor device Granted JPS58169949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57052629A JPS58169949A (en) 1982-03-30 1982-03-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57052629A JPS58169949A (en) 1982-03-30 1982-03-30 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS58169949A JPS58169949A (en) 1983-10-06
JPH0250623B2 true JPH0250623B2 (en) 1990-11-02

Family

ID=12920106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57052629A Granted JPS58169949A (en) 1982-03-30 1982-03-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58169949A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60154646A (en) * 1984-01-25 1985-08-14 Hitachi Micro Comput Eng Ltd Semiconductor device
JPS61137334A (en) * 1984-12-07 1986-06-25 Mitsubishi Electric Corp Semiconductor device
US4829362A (en) * 1986-04-28 1989-05-09 Motorola, Inc. Lead frame with die bond flag for ceramic packages

Also Published As

Publication number Publication date
JPS58169949A (en) 1983-10-06

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