JPH0726841Y2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a semiconductor integrated circuit, and more particularly to a method for ground wiring on a semiconductor integrated circuit.

[Conventional technology]

Conventionally, in the ground wiring method on this kind of semiconductor integrated circuit (hereinafter referred to as IC), when there is one ground terminal, as shown in FIG. 4, wiring is generally carried out from the bonding pad to all regions. is there. On the other hand, in recent years, along with the increase in functions, the number of terminals has increased, and ICs with multiple ground terminals have appeared from the viewpoint of measures against nozzles.

[Problems to be solved by the invention]

As the above-mentioned IC having a plurality of ground terminals, a method is adopted in which one ground wiring region and another ground wiring region are separately wired as in the case of FIG. According to this method, one of them is used properly such as for a large current, and there is an effect that a potential change of one suppresses the influence on the other. But,
When this method is viewed from the actual mounting side, the effect is obtained when the ground wiring on the printed board is taken from the same wiring as shown in FIG. 6, but when the ground wiring is supplied from another route as shown in FIG. However, the change in the electric potential of the printed board adversely affects the operation on the IC. That is, a change different from the potential change inside the IC is applied from different ground terminals.

[Means for solving problems]

The grounding wiring method for an IC according to the present invention has a plurality of grounding terminals.
In the IC, a plurality of bonding pads on the IC of each ground terminal are formed, each bonding pad is defined for each path, and ground wiring is formed so as to form a pair between each ground terminal.

That is, the semiconductor integrated circuit according to the present invention has a first ground terminal and a second ground terminal, and further, on the integrated circuit chip,
The first and second bonding pads connected to the first ground terminal and the third and fourth bonding pads connected to the second ground terminal are provided, and the first and third bonding pads are provided.
The first ground wiring connected to the bonding pad and the second ground wiring connected to the second and fourth bonding pads are provided.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram of an embodiment of the present invention. The semiconductor integrated circuit of the present embodiment includes an IC chip 11, bonding pads 12, 12 ', 13, 13', ground wirings 14, 15, and ground terminal 1.
7, 17 'and bonding wires 16, 16', 18, 18 '. Bonding pads 12 and 12 'and 13
And 13 'are grounded by independent grounding wirings 14 and 15, respectively. The ground terminal 17 is the bonding wires 16 and 18
Connected to the bonding pads 12 and 13 respectively via
The ground terminal 17 'is connected to the bonding pads 12 and 13 via bonding wires 16' and 18 ', respectively.

[Second Embodiment] FIG. 2 is a layout diagram of a second embodiment of the present invention. This embodiment has two ground terminals and three bonding pads corresponding to each ground terminal, 21 is an IC chip, 22, 23, 24, 2
2 ', 23', 24 bonding pads 22 and 22 ', 23 and 2
3 ', 24 and 24' are wired by independent ground wirings 25, 26 and 27, respectively.

FIG. 3 is a layout diagram of the third embodiment of the present invention. This embodiment is an example of a ground wiring double-layered structure, and each of the two ground terminals has two bonding pads, and the bonding pads 32 and 32 'are the ground wiring of the first layer. 33 and 33 'are wired by the ground wiring of the second layer. Although not shown, in FIGS. 2 and 3, the ground terminals are provided in the same manner as in FIG. 1 and are connected to the corresponding bonding pads.

[Effect of device]

As described above, the present invention provides an independent ground wiring between a plurality of ground terminals, and by providing a bonding pad corresponding to each ground wiring, the influence of a potential change generated inside the IC chip, for example, In addition to the effect on the noise caused by the large current and the mutual noise between the input system circuit and the output system circuit, there is an effect of suppressing the influence of a similar potential change given to the plurality of ground terminals from the wiring on the mounting.

The method according to the present invention can also be applied to power supply wiring.

[Brief description of drawings]

1 is a layout diagram of an embodiment of the present invention, FIG. 2 is a layout diagram of a second embodiment of the present invention, FIG. 3 is a layout diagram of a third embodiment of the present invention, and FIGS. Conventional layout diagrams, FIGS. 6 and 7 are layout diagrams on a printed board in a mounted state for explaining the layout diagrams of FIGS. 1 to 5. 11,21,31,41,51 ... IC chip, 12,12 ', 13,13', 22,22 ',
23,23 ', 24,24', 32,32 ', 33,33', 43,53,53 '... Bonding pad, 14,15,25,26,27,34,35,42,52,52' … Grounding wire, 62,73,73 ′… Grounding wire on printed board, 74… Wiring of printed board, 61,71… IC, 62,72… IC terminal, 17, 1
7 '... ground terminal, 16, 16', 18, 18 '... bonding wire.

Claims (1)

[Scope of utility model registration request] 1. A first and second grounding terminal, which is connected to the first and second bonding pads connected to the first grounding terminal and the second grounding terminal on an integrated circuit chip. Third and fourth bonding pads are provided, and the integrated circuit chip further connects a first ground wire connecting the first and third bonding pads to the second and fourth bonding pads. A semiconductor integrated circuit comprising: