JPH0250627B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a complementary form of the master slice format.
The present invention relates to a MOS integrated circuit device, and particularly to a method of configuring a memory element in an internal gate region.

Master slice type integrated circuits are classified into MOS type and bipolar type depending on the semiconductor devices that constitute them. Even in master slice integrated circuits,
There is a trend toward higher integration. The moss shape is generally advantageous for high integration.
Among these, CMOS master slice integrated circuits, which are composed of complementary MOS transistors (referred to as CMOS), are becoming mainstream because they have the advantage of low power consumption, which becomes a problem when the circuits are highly integrated.

FIG. 1 is a schematic plan view showing a chip structure generally employed in a master slice type integrated circuit device. In the figure, 11 to 14 are peripheral blocks, 21 to 24 are internal gate regions, and 31 to 3 are
3 is a wiring belt. Circuit elements such as transistors are regularly arranged in the internal gate area.
By forming contact holes and wiring,
Various logic gates are configured. In Figure 2, the first
An enlarged plan view of the vicinity of the internal gate region 22 shown in the figure is shown. In FIG. 2, 22 is an internal gate region, 31 and 32 are interconnection bands adjacent thereto, and 10
0 and 90 are respectively in wiring bands 31 and 32,
10 is a logic gate configured in the internal gate area 22, and 101 to 104 are vertical wires connected to the input/output terminals of the logic gate 10. It is. As shown in FIG. 2, the input/output terminals of the logic gate 10 and the wires in the wire bands 31 and 32 are connected by vertical wires, the vertical wires are on a vertical grid, and the vertical grid spacing is constant. is normal.

An example of a CMOS master slice type integrated circuit is shown in FIGS. 3-8. FIG. 3 shows the internal gate region 22 and the wiring bands 31 and 32 adjacent thereto. In the internal gate region 22, 41 to 48 are the gates of p-channel transistors, 141 to 148 are the gates of n-channel transistors, 60 is the source/drain region of the p-channel transistor, and 80 is n-channel transistor gate.
Source and drain regions of channel transistors,
Reference numerals 51 to 58 are regions for connecting substrates of p-channel transistors, 71 to 78 are regions for connecting substrates to n-channel transistors, and 91 to 98 and 101 to 108 are vertical lattices in wiring bands 32 and 31, respectively.

In addition, −, −, −, shown in FIG.
The cross-sectional view at −, − is shown as an n-well
A silicon gate CMOS structure is shown as an example in FIGS. 4, 5, 6, 7, and 8, respectively. 4-8, 41-48 are gates of p-channel transistors, 141-148 are gates of n-channel transistors, 60 is a source/drain diffusion region of a p-channel transistor, and 80 is a source/drain diffusion region of an n-channel transistor. , 201 is a p-type silicon substrate as a substrate of an n-channel transistor, 202 is an n-type well diffusion region as a substrate of a p-channel transistor, and 51 to 58 are p-type silicon substrates.
Diffusion regions of the same conductivity type are in the substrate of the channel transistor (n-type well diffusion region), 71 to 78 are the substrate of the n-channel transistor (p-type silicon substrate)
are diffusion regions of the same conductivity type, 203 is a thick oxide film for isolation between elements, and 204 is a gate oxide film.

That is, as is clear from FIGS. 3 to 8, the complementary integrated circuit in this example is a p-channel
An internal gate region 22 obtained by arranging a region (hereinafter referred to as a unit cell) having a pair of a MOS transistor and an n-channel MOS transistor adjacent to each other and a wiring band 3 adjacent thereto.
1, 32 in part, and a structure in which the vertical wiring pitch matches the width of the unit cell and the internal gate region in the wiring band, and for each unit cell,
Regions 51 to 58 are provided near the p-channel MOS transistor for supplying a positive power supply potential to the substrate of the transistor, and a region 71 is provided near the n-channel MOS transistor for supplying a ground power supply potential to the substrate of the transistor. The structure is characterized by the provision of 78 to 78.

FIG. 9 shows the wiring in the internal gate region shown in FIG. 3 when a three-input NOR circuit having input terminals 111, 112, 113 and an output terminal 114 as shown in FIG. 10 is configured as an example. 4 is a diagram schematically showing connections with each area shown in FIG. 3. FIG. In FIG. 9, 111 to 118 are wiring lines, and black circles on the wiring lines indicate connections with each area shown in FIG. 3. 111-114 are NOR
The input/output wiring of the circuit is an internal wiring 116, a positive power supply wiring 117, and a ground power supply wiring 118.

As shown in FIG. 3, this example adopts a structure in which transistors are arranged in strip-shaped source/drain regions 60 and 80, and there is no isolation region between the transistors. Therefore, the same internal gate region 2
Second, when two or more logic gates are arranged, electrical isolation between the logic gates is required. FIG. 11 shows a method of separating logic gates in this example. In FIG. 11, 111, 112, 113 shown in FIG. 12 are added to the internal gate region 22 shown in FIG.
When a first 3-input NOR circuit with 211, 212, 213 as input terminals and 214 as an output terminal is placed adjacent to each other. shows.
In the figure, 111 to 114 are the first three inputs.
In the input/output wiring of the NOR circuit, 211 to 214 are the input/output wiring of the second 3-input NOR circuit, and 11
7 is the positive power supply wiring, 118 is the ground power supply wiring, 601
is the wiring connected to the positive power supply wiring 117, and the wiring 1
14 and 211, and 602 is the ground power supply wiring 1.
The wiring 18 is connected to the gate of an n-channel transistor located at a position corresponding to the gate connected to the wiring 601.

As shown in FIG. 11, the gates of the p- and n-channel transistors located between both three-input NOR circuits are fixed to the positive power supply potential and the ground power supply potential, respectively, so those transistors are in a cut-off state.
The 3-input NOR circuits are electrically isolated.

Furthermore, in CMOS integrated circuits, the latch-up phenomenon caused by parasitic bipolar transistors often becomes a problem. The latch-up phenomenon occurs when the substrate of an n-channel transistor becomes higher than the ground power supply potential or the substrate potential of a p-channel transistor falls below the positive power supply potential due to charge injected into the bulk for some reason. It is. Therefore, as a method for preventing latch-up, a method has been proposed in which the substrate potential of the transistor is fixed to the positive power supply potential or the ground power supply potential. FIG. 13 shows a method of fixing the substrate potential in this example. In FIG. 13, 117 is a positive power supply wiring, 118 is a ground power supply wiring, 700 is a wiring connected to the positive power supply wiring 117 and connected to substrate connection regions 51 to 58 of the p-channel transistor shown in FIG. 701 is a wiring connected to the ground power supply wiring 118 and connected to the substrate connection regions 71 to 78 of the n-channel transistors. Wiring 70
0,701, the substrates of the n- and p-channel transistors can be fixed to the ground power supply potential and the positive power supply potential for each transistor, and the latch-up phenomenon can be prevented from occurring.

A conventional method for configuring a memory element in the CMOS master slice type integrated circuit described above will be explained.

Figure 14 shows the conventional 6-transistor configuration.
A circuit of a CMOS storage element is shown. In the figure,
T ₁₄₃ to _{T 146} are n-channel transistors having gates 143 to 146, respectively; T ₄₃ and T ₄₄ are p-channel transistors having gates 43 and 44, respectively; 123 and 124 are wirings for forming a memory circuit; and 117 is a positive 118 is a ground power supply wiring; 120 is an X-direction selection line (hereinafter referred to as a word line) for memory elements arranged in a matrix; and 121 and 122 are Y-direction selection lines (hereinafter referred to as a digit line).

When a high (“H”) level potential is applied to the word line 120, the transfer gates T ₁₄₃ ,
T ₁₄₆ becomes conductive and digit lines 121,
122 can be used to read and write to this memory element.

FIG. 15 shows an example in which the circuit shown in FIG. 14 is constructed on the internal gate region 22 shown in FIG. 4. In the figure, 101-107 and 91-97
42 to 47 are gate polysilicon gates of p-channel transistors; 60 are source and drain regions of n-channel transistors; 142 to 147 are vertical wiring lines;
80 is the gate polysilicon of the n-channel transistor, 80 is the source/drain region of the n-channel transistor, 123 and 124 are wirings for configuring the memory circuit, 117 is the positive power supply wiring, 118 is the ground power supply wiring, 120 is the word line, 121,1
22 is a digit line. However, in FIG. 15, 51 to 59 and 72 to 78 in FIG.
The description of the area corresponding to is omitted for the sake of simplicity.

Gate polysilicon 42, 45 and 72, 77
were connected to the positive power supply wiring and the ground power supply wiring, respectively, to provide electrical isolation from the adjacent memory elements.

From FIG. 15, if the memory element is configured in the internal gate region in the conventional circuit, it will occupy five vertical lattice spaces and leave the gate polysilicon 46 and 47 unused, which reduces the efficiency of element usage. You can see that it is low.

The present invention has been made in view of the above points, and an object thereof is to improve the usage efficiency of elements and provide a memory element with high integration density.

FIG. 16 shows a circuit diagram of an embodiment of the present invention. In the figure, T ₁₄₃ to _{T 145} are n-channel transistors having gate polysilicon 143 to 145, respectively, T ₄₃ to _{T 45} are p-channel transistors having gate polysilicon 43 to 45, respectively, and 123 and 124 constitute memory elements. 117 is a positive power supply wiring, 118 is a ground power supply wiring, 119 and 120 are word lines, 121 and 1
22 is a digit line.

A feature of this embodiment is that there are two word lines, so that transistors T ₁₄₃ and T ₄₅ are N-channel transistors and P-channel transistors (in the conventional case, both are N-channel transistors). It lies in what you can do. That is, reading from the storage element,
Writing to the memory element is performed by setting the word line 120 to an "H" level potential and the word line 119 to a low ("L") level potential, thereby making the transfer gates T ₁₄₃ and T ₄₅ conductive. Can be done.

An example in which the circuit of this embodiment shown in FIG. 16 is configured in the internal area 22 shown in FIG.
As shown in the figure. 101-106 and 91-96 are vertical lattices, 42-46 are gate polysilicon gates of p-channel transistors, 60 are source/drain regions of p-channel transistors, 142-146 are gate polysilicon gates of n-channel transistors, 80
123 and 124 are wirings for forming a memory circuit, 117 is a positive power supply wiring, 118 is a ground power supply wiring, 119 and 120 are word lines, 121 and 1 are the source and drain regions of the n-channel transistor,
22 is a digit line. However, in FIG. 17, descriptions of areas corresponding to 51 to 58 and 71 to 78 in FIG. 4 are omitted for the sake of simplicity.

As can be seen from FIG. 17, according to this embodiment, the usage efficiency of circuit elements such as transistors can be higher than that of the conventional one, and as a result, only four vertical lattice spaces are occupied in the internal area, and the integration density is higher than that of the conventional one. You can see that it can be made higher.

In the above examples, the
Although a CMOS master slice integrated circuit has been described, the present invention is also effective for other types of CMOS master slice integrated circuits.
This is clear from its circuit configuration.

As described above, the present invention is extremely effective for increasing the degree of integration when configuring storage elements on a CMOS master slice type integrated circuit.

[Brief explanation of the drawing]

Fig. 1 is a schematic plan view showing a chip structure generally employed in master slice type integrated circuit devices, Fig. 2 is an enlarged plan view of the vicinity of the internal gate region in Fig. 1, and Fig. 3 is a CMOS master slice. FIGS. 4, 5, 6 are plan views showing the main parts near the internal gate region of an example of an integrated circuit device,
Figures 7 and 8 are - of Figure 3, respectively.
The enlarged cross-sectional view at line, - line, - line, - line, - line, Fig. 9 is 3 using this configuration.
A plan view showing an example of an input NOR logic gate circuit, FIG. 10 is a logic circuit diagram thereof, and FIG. 11 is a plan view showing an example of forming an input NOR logic gate circuit.
FIG. 12 is a plan view showing an example of a configuration of a logic gate circuit, FIG. 12 is a logic circuit diagram thereof, FIG. 13 is a plan view showing a method of fixing substrate displacement in this example, and FIG.
A circuit diagram showing a conventional example of a memory element with a CMOS configuration,
FIG. 15 is a plan view showing a conventional example in which the circuit shown in FIG. 14 is formed using the configuration shown in FIG.
FIG. 7 is a plan view showing an embodiment of the present invention in which the circuit shown in FIG. 16 is formed using the configuration shown in FIG. 3. In the figure, 22 is an internal gate region, 41 to 4
8 is the gate of the p-channel MOS transistor, 5
1 to 58 are positive power supply voltage supply regions, 71 to 78 are ground power supply voltage supply regions, 141 to 148 are gates of n-channel MOS transistors, 60 are source and drain regions of p-channel MOS transistors,
80 is the source of the n-channel MOS transistor.
a drain region, 119 and 120 are word lines,
121 and 122 are digit lines, T ₁₄₃ is the first
T ₄₅ is the second transfer gate. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. In a complementary MOS integrated circuit device using a master slice method, a memory circuit formed mixed with an original logic circuit in an element formation region, comprising a pair of p-channels.
An inverter comprising a first unit cell, comprising an internal gate region in which a plurality of unit cells each having a MOS transistor and an n-channel MOS transistor are arranged side by side, and a wiring band provided adjacent to the internal gate region. and a second inverter constituted by the above-mentioned unit cells, in which a pair of word lines are provided which operate complementary to each other, and one of the word lines is composed of an n-channel MOS transistor. A first transfer gate connected to the output terminal of an inverter constituted by a first unit cell is driven, and a p-channel is connected to the other word line which works complementary to the one word line.
A complementary MOS integrated circuit device comprising a MOS transistor and driving a second transfer gate connected to an output terminal of an inverter constituted by the second unit cell. 2. A patent claim characterized in that each unit cell is provided with a region for supplying a positive power supply voltage to the substrate of a p-channel MOS transistor section and a region for supplying a ground power supply voltage to the substrate of an n-channel MOS transistor section. Complementary MOS integrated circuit device according to item 1.