JPH0250736A - Abnormality detecting system for multiplexed device - Google Patents

Abstract

PURPOSE:To quickly detect a failed device by forcedly regarding a lower rank device generating no response as an error at the time of receiving a normal response from either one of lower rank devices when a multiplexed device is failed. CONSTITUTION:Two memories, i.e. a common memory CM1 to be a master memory and a common memory CM2 to be a slave memory, are included in a multiplexed lower rank device. A common memory adaptor (CMA) is provided with an abnormality detecting circuit D to detect abnormality in the CM1 and CM2 to be the lower rank device. When abnormality is generated in the CM1 and CM2 to be the multipliexed lower rank device, the report of the error to the CMA is validated/invalidated in accordance with a condition. When the abnormality can not be reported at the time of a normal end, no response is detected as a matter of course, but when an error is reported before the normal end, the report is neglected so as to be treated similarly to no response. Thus, abnormality can be simply and easily detected.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Prior Art (Figures 7 to 12) Means for Solving the Problems to be Solved by the Invention (Figure 1) Working Examples (Figures 2 to 6) Effects of the invention [Summary] Regarding the abnormality detection method of multiplexing equipment, when a multiplexed equipment fails, any one of the lower-order equipment
The purpose of this system is to detect a malfunctioning device quickly by forcibly treating a non-responsive lower-level device as an error when a normal response is received from the lower-level device. In a multiplexing device, the multiplexing device performs synchronous operation using a clock sent from the device, and the lower devices each individually report the completion of the operation in response to a command issued from the higher device along with the completion status.
The upper device is equipped with an abnormality detection means for detecting an abnormality in the lower device, and if there is an abnormality report from the lower device that is faster than a normal response, it is ignored and it is assumed that there has been no response, and the lower device The device is configured such that when any one of the normal responses is received, any device that does not respond is forcibly treated as abnormal and controlled.

[Industrial application field]

The present invention relates to an abnormality detection method in a multiplexing device, and in particular, in a computer or the like, when a multiplexed device breaks down, the faulty device can be immediately disconnected, so that the faulty device can be detected as quickly as possible. This invention relates to an abnormality detection method in a multiplexing device.

[Conventional technology]

With the recent remarkable development of the information society, demands for high speed and high reliability of systems are becoming more and more important.

Conventionally, in response to this demand, a method has generally been adopted in which systems are multiplexed so that if one system goes down, the other system can perform the work.

Recently, as non-stop computers, each unit has been made into components from the design stage and these have been multiplexed. If one part fails, the failed part is degenerated and the hardware is built in to carry out the work. It has become.

However, in any case, when disconnecting or switching a faulty system or part, it is important to do this in a short time.

- In boat fishing, when a higher-level device detects a failure in a lower-level device, it is detected by some kind of error or normal report signal from the lower-level device, and if the lower-level device cannot return a response, it does not respond even after waiting for a certain period of time. If is not returned (
(timeout) Many methods are used to treat this as a failure of the lower-order device.

Hereinafter, a conventional example will be explained based on the drawings.

FIG. 7 is a diagram showing a conventional multiplexing device.

In the figure, CMA is a common memory adapter, and a timer T1 flip-flop FF, an inverter INV, etc. are provided inside this adapter.

This CMA is connected to the CPU (A) and CPU
(B) Multiplexed CM (common memory) connected to the lower level in synchronization with the clock from the CPU according to a request from the CPU
(Multiplexed common memory CM)
It is a device that performs control for reading out CM data and sending it to a higher-level device.

As the multiplexed CM, CM (1) which is a mask memory and CM (2) which is a slave memory are provided.

BUS■ is a bidirectional data bus between the CMA and CM(1) and CM(2), and when the CMA sends a command, the data length and memory address within the CM are sent from the CMA.

Furthermore, when the CMA sends out data, the (hrite) data is sent out together with the DATV signal (data valid signal).

When the CMA reads CM (common memory) upstream data, read data is loaded together with the DSEND signal (data valid signal) sent from the mask CM.

Next, the operation shown in FIG. 7 will be explained based on FIGS. 8 to 12.

(1) In the write sequence to CM, CM (1
) and CM (2) are both normal (see Figure 8). If the CMA's host device (in this example, CPU (A), CPU
(B) (8) sends data to the CMA through bus (2) in synchronization with the synchronization signal.

A control circuit within the CMA that receives the data prioritizes various requests to the CM (refresh requests, patrols, and other CPU requests).

Then, if the conditions are met, the memory address (
ADD), data length (LNG) to bus (BUS)
Write the CMD (command) signal ■ to
e) and turn on the CMDV (command valid) signal ■.

After that, turn off the CMDV signal and send the write data to the bus (BUS) signal.
Turn on and send the first data.

Only the number of data indicated by LNG (length) is sent (
In this example, 1 byte data is repeated 8 times and sent out in synchronization with the system clock), and when the sending is finished, the DATV (data valid) signal is turned off.

After that, end signals (END#O and END#1) and status signals (ST
AT#O and 5TAT#1) are sent to the CMA.

In this example, since both CM (1) and CM (2) are normal, there is an END signal within the predetermined CMA busy time, and the cycle moves directly to the next cycle.

(2) In the read sequence from CM, C
When both M (1) and CM (2) are normal (see Figure 9), when reading CM, the same operation as writing is performed, but when sending data and sending the DSEND (data sending) signal, MAST output from flip-flop FF
Only the CM that receives the ER signal (■) sends it.

In this example, CM (1) is a mask and CM (2) is a slave, but if the states of the flip-flops are reversed, CM (2) becomes a mask and CM (1) becomes a slave.

When the CMA receives a read request from the CPU, it takes the same procedure (priority) as above and sends the memory address (ADD) and data length (LNG) to the bus (BUS) ■ and the CMD signal ■ to the CM. Read
) and turn on the CMDV (command valid) signal ■.

Thereafter, the CMDV signal is turned off, the BUS is placed in a receiving state, and the DSEND signal (2) is waited for.

When the receiver receives the DSEND signal, the receiver receives the data on the BUS at that time.

In this way, in synchronization with the synchronization signal (system clock), it receives and receives data sequentially sent together with the DSEND signal, and waits for the END signal (2) and the status signal (3).

In this example, after the data has been sent to the CMA eight times, the EN
D#0.5TAT#01 END#1.5TAT#1 is output, so everything is normal.

Therefore, when the CMA busy time ends, the next cycle begins.

(In the read sequence from 31CM, CM
When (1) is normal and CM (2) is abnormal (see Figure 10) In this example, 8-byte data is read in 8 times in the same manner as above. At this time, since CM (1) is normal, the END#0 signal and 5TA are sent at the same time as the 8th data transmission.
Give a T signal.

However, the slave memory CM (2) becomes abnormal during the third data transmission and issues END#1 and 5TAT signals.

In this case, the 5TAT signal ■ consists of 2 bits; for example, if it is "00", it is normal with no abnormality, if it is 01", it is a 1-bit error, and if it is "10", it is a 2-bit error.
If it is "1)", it is considered abnormal.

That is, 1-bit errors and 2-bit errors are not treated as abnormalities, and only the case of "1", which is an error in the control circuit (for example, a parity error in a counter, etc.), is cut as abnormal.

Therefore, in this example, CM (2) is abnormal at 61)'', but since CM (1) is normal, CM (2)
The next cycle is executed using only CM (1). That is, the 5CUT (slave cut) signal is turned on to disconnect CM (2).

(In the read sequence from 41CM, CM
(1) is abnormal and CM (2) is normal (see Figure 1)) In this example, slave memory CM (2) is normal and master memory CM (1) is abnormal, so the flip-flop FF After reversing the states, making CM (1) the slave and switching CM (2) to the mask,
Turn on the 5CUT signal to disconnect this slave memory CM (1).

(In the read sequence from 51CM, CM
(1) Normal, CM (2) No response (abnormal) (first
(See Figure 2) In this example, mask memory CM (1) sends out an end signal with the 8th data send, so it is normal.
Slave memory CM (2) remains completely unresponsive (abnormal).

In this case, the timer T in the CMA operates, and after the timer T times out, the slave memory CM (2)
Isolate it as an abnormality.

[Problem to be solved by the invention]

The above-mentioned conventional devices had the following drawbacks.

That is, when lower-level devices are multiplexed, there may be a normal response from one device and no response from the other device (for example, see the example in FIG. 12 above).

In such a case, the host device has to wait for a certain period of time (the time until the timer times out) in order to know the completion status of both, which has the drawback of degrading the performance of the host device.

The present invention was made in order to solve these conventional drawbacks, and it is possible to determine that one lower-level device has completed the sequence normally (an error of 2 bits or less is considered normal) when a response is returned. This is intended to prevent the performance of the multiplexer from deteriorating by treating the device as having failed if there is no response from the other device, or if it is deemed that there is no response. .

[Means to solve the problem]

In order to achieve the above object, the present invention is as follows.

FIG. 1 is a diagram showing the principle of an abnormality detection method in a multiplexing device according to the present invention, and the present invention will be explained in detail below based on this diagram.

Two memories as multiplexed sub-devices, i.e.
A common memory CM (1) as a mask memory and a common memory CM (2) as a slave memory are provided.

Various commands are executed in synchronization with a clock sent from a host device connected to bus (2), such as a central processing unit (CPU).

Also, inside the CMA (Common Memory Adapter),
CM (1) which is a lower-level device with an abnormality detection circuit AD installed
and CM (2).

CM (1) and CM (2) send end signals END#O and END#1 (
Each bit is 1 bit, for example, it is "0" when it is not completed, and it is "1" when it is completed), and 5TAT, which is a status signal.
#0 and 5TAT#1 (consists of 2 bits, B is “00” when normal, B is “01” when there is a 1-bit error, B is “10” when there is a 2-bit error, and B is “1” when there is an abnormality in the control circuit.
)”) to report.

Based on this report, the abnormality detection circuit AD in CMA
Detect anomalies.

In this case, if an error report is received faster than a normal response, it will be ignored and it will be assumed that there was no report, and as soon as a normal response is received from any one of the lower devices, the non-responsive device (
(including those ignored as above) are forcibly treated as errors to detect anomalies.

[Effect]

CM (1) and CM (2), which are multiplexed lower-level devices
When an abnormality (error) occurs in the CMA, there are cases where the error can be reported to the CMA and cases where it is not possible.

If an error cannot be reported during normal termination, it will naturally be detected as no response, but if an error is reported before normal termination, this will be ignored.
This is handled in the same way as the case of no response as described above.

This allows for simple and easy abnormality detection.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. Second
The figure is a diagram showing an abnormality detection method in a multiplexing device according to an embodiment of the present invention.

CPUI and CPU2 are each CMA (common
It is a host device for the CMA (memory adapter), and is connected to the CMA via a bus.

In addition, multiplexed common memories are provided as lower devices of the CMA, and one of them, CM (1), is used as, for example, a master memory, and the other one, CM (2), is used as, for example, a slave memory. Multiplexed.

The common memory adapter CMA includes an abnormality detection circuit AD for detecting an abnormality in the common memories CM (1) and CM (2), a flip-flop FF for switching between the mask memory and the slave memory, and a flip-flop for switching between the mask memory and the slave memory. Inverter I for inverting the FF output signal
NV, control circuit, etc. are provided.

The connection between the CMA and the common memory is the same as in the conventional example described above, and various signals are also the same.

That is, BUS is a bidirectional bus, ■CMD V (common valid) signal is a command valid signal sent from CMA to common memory CM, and ■DATV (data valid) signal is sent from CMA to common memory CM. ■DSEND signal (data sending signal) is a data valid signal when sending data from CM to CMA (only master memory can send data), ■CMD is a data valid signal for sending data from CM to CMA.
This is a command signal sent from the CM to the CM.

Also, ■clock (clock) is a common memory clock line sent from CMA, and the clock sent from this clock line causes CMA and CM (1
) and CM (2) operate synchronously.

■5TAT#O and 5TAT#1 are status signals each consisting of 2 bits, ■END#0 and END#1
are each end signals (completion signals).

The @l5cUT (slave cut) signal is used to disconnect either CM (1) or CM (2) which has become a slave CM in the event of an abnormality.

OMASTER and @5LAVE are CM (1) and CM (
This is a signal for using one of the two as a mask and the other as a slave, and is a signal output from the flip-flop FF.

FIG. 3 is a detailed diagram of the abnormality detection circuit of FIG. 2.

In the figure, INV (1) to INV (4) are inverters, NAND (1) to NAND (5) are NAND circuits, AND (1) to AND (4) are AND circuits, and JK-1 to JK- 4 is a JK flip-flop, D is a D flip-flop, MD is a mask side decoder, and SD is a slave side decoder.

Also, as input signals, the two bits of ■5TAT#O are 5TATO#O and 5TAT1#O, and ■5TAT#
2 bits of 1 are 5TATO#1 and 5TAT1#1,
■END#0 and ■END#1 become END#O and END#1, respectively.

Next, specific examples shown in FIGS. 4 to 6 will be explained.

(1) In the read sequence from CM, master memory CM (1) is normal and slave memory IJcM
When (2) is no response (abnormal) (see Figure 4).

In this case, data is read in the same manner as in the conventional example.

In other words, the sending of data and the sending of the DSEND signal are performed by the mask signal that is turned on by the receiving CM (OMAS in this figure).
At TER, only CM (1) (masked) transmits.

The CMA receives a read request (R
ead request), it takes a predetermined procedure and sends the CM the memory address (ADD>, data length (LN
G) to BUS■, read CMD signal■
and turn on the CMDV signal ■.

After that, turn off the CMDV signal and wait for the DSEND signal ■.

When the DSEND signal is received, the data on the BUS at that time is received. In this way, when data of 1 byte is received 8 times for each system clock, an END signal (END#O) and a status signal (STAT) are sent from the mask memory CM (1). Ru.

However, at this time, there is no response from CM (2), which is the slave memory (no END#1 signal and no 5TAT#1 signal).

Therefore, since the abnormality detection circuit detects this at this time, based on this, 5CUT (slave cut) is turned on and &CM (2) is cut off in the slave memory.

After all, if there is no response, it is assumed that the abnormal state is in an abnormal state and the abnormal memory is disconnected without waiting for the timer to time out as in the conventional case.

Then, the next cycle is executed using only the remaining memory.

In the read sequence from f21CM, if mask CM <1) normal, slave CM (2) abnormal (
In this case, CM (1) is normal and CM (2) is abnormal (reported). As in this example, when an abnormality occurs during data transmission and the abnormality detection circuit detects an abnormal signal (END#1 B''1)'' signal), it ignores this and
Only when there is a normal response (END #0 and 5TAT signals) from CM (1), it is treated as if there was no END signal from CM (1) at that time.

Therefore, in this example, since the abnormal signal of END#1 is ignored, 5CUT is generated in the cycle after END#0 is issued.
Turns ON and disconnects slave memory CM (2).

(In the read sequence from 31CM, slave memory CM (2) is normal and master memory CM (
If 1) is abnormal In this example, the mask memory CM (
This is a case where an abnormal signal (STATB "1)") is issued from the slave memory CM (1), but a normal end signal is issued from the slave memory CM (2).

At this time, the abnormal signal issued from CM (1) is ignored.

Then, since the master memory is abnormal, the state of the flip-flop FF is reversed, the mask and slave are reversed, and the new slave memory is separated.

That is, the slave memory CM(1) is separated with CM(2) as a mask and CM(1) as a slave.

The operation of the abnormality detection circuit shown in FIG. 3 is as follows.

The END signal is “0”” when it is not completed, and “1, ′” when it is completed normally.
5TAT consists of 2 bits, “OO” is normal, 01”
is a 1-bit error “10” is a 2-bit error 1)”
is abnormal (up to 2-bit error is considered normal).

(1) When both the mask and slave are normal (Figures 8 and 9)
(See figure) The input signals are END#OB "1" (meaning that the END#0 bit is "1"), 5TAT'O#0 (STA
1st bit of T#O) B″0″, 5TATI#O(ST
2nd bit of AT#O)B “0”, END#IB”1”
, 5TATO#IB"O', 5TATO#IB"O', 5TATO#IB"O'
It is “0”.

Due to this signal, the outputs of NAND (1) to NAND (4) all become “0”, and the output of NAND (5) becomes “0”.
1", the outputs of AND(1) to AND(4) all become "0".

Therefore, the decoder outputs on the mask side and slave side are B“
00'' and a signal indicating normality is output.

(2) When both the mask and slave are normal, but the master memory has a 1-bit error and the slave memory has a 2-bit error (see Figures 8 and 9), the input signal is END#.
OB"1", 5TATO#OB"l", 5TAT1#O
B "0'", END#IB'l", 5TATO#
1B10", 5TAT1#IB"1".

Due to this signal, the outputs of NAND (1) and NAND (4) are “1”, and the outputs of NAND (2) and NAND (3) are “1”.
The output of NAND (5) is “0” and the output of NAND (5) is “1”.
”.

Therefore, the outputs of AND (1) and AND (4) are "1" and the outputs of AND (2) and AND (3) are "0".
Therefore, the output of the mask side decoder MD is B“01”
Therefore, the output of the slave side decoder SD becomes B "10".

However, in this case, since it is a 1-bit error and a 2-bit error, it is treated as normal in this example.

(3) When the mask memory is normal and the slave memory is abnormal (see Figure 5), the input signals are END#I B''1'', 5TATO#OB
@O", 5TAT1#OB 0", END#IB" 1
″, 5TATO#IB “ 1 ”, 5TAT1#I
B is “1”.

Due to this signal, the outputs of NAND (1) and NAND (2) become "0", the outputs of NAND (3) and NAND (4) become "1", and the output of NAND (5) becomes "1".

Therefore, the output of AND (1) and AND (2) is 0
'', the outputs of AND (3) and AND (4) become "1", so the output of the mask-side decoder MD is B "00", which is normal, and the output of the slave-side decoder SD is B "1)", which is an abnormal signal. becomes.

In the above embodiment, a case has been described in which one of the common memories is normal and the other is non-responsive (abnormal), but it is possible that both lower-level devices become non-responsive at the same time.

However, since such an abnormality is considered to be extremely rare, in that case it will be detected by the time-up of a timer as in the past.

〔Effect of the invention〕

As explained above, the present invention has the following effects.

Even if one of the multiplexed devices (for example, memory) fails such that it becomes unresponsive, it is possible to perform a disconnection operation without degrading performance.

Further, even if the completion reports of the multiplexed devices arrive at different timings, there is no need to store their error statuses, etc., and the circuit can be simplified.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the present invention, Fig. 3 is an example of an abnormality detection circuit in the present invention, and Figs.
FIG. 6 is an explanatory diagram of the operation of the present invention, FIG. 7 is a configuration diagram of the conventional example, and FIGS. 8 to 12 are explanatory diagrams of the operation of the conventional example. CMA - Common memory adapter AI) - m - Abnormality detection circuit FF - Flip-flop INV - - Inverter CM (LL - - Common memory (master memory) CM
(2) - Common memory (slave memory) N A N
D-11 NAND circuit AND-AND circuit Ml)-11 Master side decoder SD-Slave side decoder JK-1 to JK-4-1-JK flip-flop D-D
Flip-flop patent applicant Fujitsu Ltd. Representative Patent Attorney Akira Yamatani Eishi Yaji

Claims (1)

[Claims] (1) Equipped with multiplexed lower-level devices, these lower-level devices perform synchronous operations using clocks sent from the higher-level device, and each lower-level device individually reports the completion of operations in response to commands issued from the higher-level device along with the completion status. In a multiplexing device that reports abnormalities in lower-level devices to higher-level devices, an abnormality detection means (A
Equipped with D), if there is an abnormality report from a lower-level device that is faster than a normal response, it will be ignored and it will be assumed that there has been no response, and when a normal response is received from any one of the lower-level devices. An abnormality detection method for a multiplexing device, characterized in that a device that does not respond is forcibly treated as abnormal and controlled.