JPH0831048B2 - Anomaly detection method for multiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Outline Industrial field of application Conventional technology (FIGS. 7 to 12) Problem to be solved by the invention Means for solving the problem (FIG. 1) Action Example (FIGS. 2 to 6) Effects of the Invention [Outline] Regarding an abnormality detection method for a multiplexing device, when a multiplexed device fails, a normal response is received from any one of the lower devices. For the purpose of promptly detecting a failed device by forcibly considering a non-responsive lower device as an error, it is equipped with multiplexed lower devices, and these lower devices operate synchronously with the clock sent from the upper device. In addition, in the multiplexing device, the lower device reports the operation end report for the command issued from the upper device together with the end status individually. If there is an abnormal report that is faster than the normal response from the lower device, it is assumed that there is no response, and when one of the lower devices receives a normal response, A device that does not respond is configured to be forcibly regarded as abnormal and controlled.

[Industrial applications]

The present invention relates to an abnormality detection method in a multiplexing device, and in particular, in a computer or the like, when a multiplexed device fails, the failed device is quickly disconnected, so that the failed device can be detected as soon as possible. The abnormality detection method in the multiplexing device described above.

[Conventional technology]

With the recent remarkable development of the information society, the demand for high speed and high reliability of the system is becoming more important.

Conventionally, a method has been generally adopted in which systems are multiplexed in response to this request, and when one of the systems goes down, the other system carries out a task.

Recently, as a non-stop computer, each unit has been made into a component from the design stage and these units have been configured to be multiplexed, and if a part fails, it should be built into hardware so that the failed part can be degenerated and work can be performed. Came to.

However, in any case, when disconnecting or switching a failed system or a failed part, it is important to perform this in a short time.

In general, when a failure of the lower device is detected by the upper device, it is performed by an error or normal report signal from the lower device, and when the lower device cannot return its response, it responds even after waiting for a certain period of time. If is not returned (timeout), it is often used to consider it as a failure of the lower device.

 Hereinafter, a specific example of the related art will be described with reference to the drawings.

 FIG. 7 is a diagram showing a conventional multiplexing device.

In the figure, CMA is a common memory adapter, inside which a timer T, a flip-flop FF, an inverter INV, etc. are provided.

This CMA is a high-level device CPU (A) and CPU (B)
In response to the request from the CPU, the data is written to the multiplexed CM (common memory) connected to the lower order in synchronization with the clock from the CPU (the shared common memory CMs all guarantee the sameness of the data), Or read the CM data,
It is a device that performs control for sending to a higher-level device.

As the multiplexed CM, CM (1) which is a master memory and CM (2) which is a slave memory are provided.

BUS is a bidirectional data bus between CMA and CM (1) and CM (2). When CMA sends a command, the data length and the memory address in CM are sent from CMA.

When the CMA sends data, write data is sent together with the DATV signal (data valid signal).

When the CMA reads CM (common memory) upstream data, read data is placed together with the DSEND signal (data valid signal) sent from the master CM.

Next, the operation of FIG. 7 will be described with reference to FIGS. 8 to 12.

(1) When both CM (1) and CM (2) are normal in the writing sequence to CM (see Fig. 8), the higher device of CMA (CPU (A) and CPU (B) correspond in this example) Sends data to the CMA through the bus in synchronization with the sync signal.

The control circuit in the CMA that receives the data receives various requests for the CM (refresh request, patrol,
Other CPU requests) takes priority.

Then, if the conditions are met, the memory address (ADD), data length (LNG) to the bus (BUS), and C to the CM.
Set MD (command) signal to write and use CMDV
Turn on the (command valid) signal.

After that, the CMDV signal is turned off, the write data is placed on the bus (BUS), the DATV (data valid) signal is turned on, and the first data is transmitted.

Only the number indicated by LNG (length) is sent (8
Byte) repeated (in this example, 1-byte data is repeated 8 times and transmitted in synchronization with the system clock), and when the transmission is completed, the DATV (data valid) signal is turned off.

After that, end signal (END) from CM (1) and CM (2)
# 0 and END # 1) and status signals (STAT # 0 and STA
T # 1) is sent to CMA.

In this example, since both CM (1) and CM (2) are normal, there is an END signal within a predetermined CMA busy time, and the process directly proceeds to the next cycle.

(2) CM (1) in the read sequence from CM
When CM and CM (2) are both normal (see Fig. 9) When CM is read, the same operation as writing is performed, but data transmission and DSEND (data transmission) signal transmission are performed from the flip-flop FF. Only the CM that received the issued MASTER signal sends it.

In this example, CM (1) is the master and CM (2) is the slave, but if you flip the flip-flop state,
CM (2) is the master and CM (1) is the slave.

When the CMA receives a read request from the CPU, the same procedure (priority) as above is followed, and the memory address (ADD) and data length (LNG) are sent to the bus (BUS).
Then, the CMD signal is set to Read and the CMDV (command valid) signal is turned on.

After that, the CMDV signal is turned off, the BUS is received, and the DSEND signal is waited for.

When the DSEND signal is received, the data on the BUS at that time is received.

In this way, in synchronization with the synchronizing signal (system clock), the data sequentially sent with the DSEND signal are received, and the END signal and the status signal are waited for.

In this example, END # is sent when data has been sent to the CMA eight times.
0, STAT # 0, END # 1, STAT # 1 are issued, so everything is normal.

Therefore, when the CMA busy time ends, the next cycle starts.

(3) In the read sequence from CM, CM (1)
Is normal and CM (2) is abnormal (see FIG. 10) In this example as well, the 8-byte data is read in eight times. At this time, since CM (1) is normal, the END # 0 signal and the STAT signal are issued at the same time as the eighth data transmission.

However, the slave memory CM (2) becomes abnormal at the time of the third data transmission and outputs END # 1 and the STAT signal.

In this case, the STAT signal consists of 2 bits,
For example, "00" is normal without any abnormality, and "01" is 1
Bit error, 2-bit error if "10", abnormal if "11".

That is, the 1-bit error and the 2-bit error are not treated as abnormal, and only the case of "11" which is a control circuit (for example, a parity error of a counter or the like) error is cut as an abnormality.

Therefore, in this example, although CM (2) is abnormal at "11", but CM (1) is normal, CM (2) is disconnected and CM (1) alone executes the next cycle. That is, SC
Turn on the UT (slave cut) signal to disconnect CM (2).

(4) CM (1) in the read sequence from CM
Is abnormal and CM (2) is normal (see FIG. 11) In this example, since the slave memory CM (2) is normal and the master memory CM (1) is abnormal, the flip-flop FF
By reversing the state of, the CM (1) is switched to the slave and the CM (2) is switched to the master, and then the SCUT signal is turned on to disconnect the slave memory CM (1) which is the slave.

(5) In the read sequence from the CM, when CM (1) is normal and CM (2) is unresponsive (abnormal) (see FIG. 12), in this example, the master memory CM (1) sends the 8th data and Although the end signal is sent normally, the slave memory CM (2) remains completely unresponsive (abnormal).

In this case, the timer T in the CMA is activated, and after the timer T has timed out, the slave memory CM (2) is disconnected as an abnormality.

[Problems to be Solved by the Invention]

The conventional device as described above has the following drawbacks.

That is, when the lower-level devices are multiplexed, one side may have a normal response and the other side may have no response (for example, see the example of FIG. 12 above).

In such a case, the host device waits for a certain period of time (time until the timer times out) in order to know both end statuses, which has a drawback of degrading the performance of the host device.

The present invention has been made in order to solve such a conventional drawback, and one of the lower devices judges that the sequence is normally completed (an error of 2 bits or less is regarded as normal) and a response is returned. The purpose of this is to consider the device as a failure when the other response is considered to be absent or absent at the timing when the other device arrives so that the performance of the multiplexing device is not degraded. .

[Means for solving the problem]

In order to achieve the above object, the present invention is as follows.

FIG. 1 is a principle diagram of an abnormality detection system in a multiplexing device according to the present invention, and the principle of the present invention will be described below with reference to this diagram.

Two memories, that is, a common memory CM (1) as a master memory and a common memory CM (2) as a slave memory are provided as the multiplexed lower devices.

Then, various commands are executed in synchronization with a clock transmitted from a host device connected to the bus, such as a central processing unit CPU.

Also, an abnormality detection circuit AD is provided in the CMA (common memory adapter), and CM (1) and CM, which are lower devices, are installed.
The abnormality of (2) is detected.

From CM (1) and CM (2), the end signals END # 0 and END # 1 to the CMA (each is 1 bit, for example, when it is not finished, it ends with "0", and then with "1"). Become)
And status signals STAT # 0 and STAT # 1 (consisting of 2 bits, B "00" for normal operation, B "01" for 1-bit error, B "10" for 2-bit error, and control When the circuit is abnormal, B "11") is sent and reported.

The abnormality detection circuit AD in the CMA detects an abnormality based on this report.

In this case, if there is an error report faster than the normal response, it is ignored and it is assumed that there was no report, and when any one of the lower-level devices receives a normal response, the device with no response (ignored as above) (Including the ones that have been specified) are forcibly regarded as errors, and anomalies are detected.

[Action]

If an error (error) occurs in CM (1) and CM (2), which are multiplexed lower-level devices, the error is reported by CMA.
May or may not be reported to.

At the time of normal termination, if no error can be reported, it is naturally detected as no response, but if an error is reported before the normal termination, by ignoring this, the above-mentioned no response is returned. It is handled as in the case.

 This makes it possible to easily and easily detect an abnormality.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an anomaly detection method in a multiplexing device according to an embodiment of the present invention.

The CPU1 and the CPU2 are host devices of a CMA (common memory adapter), and are connected to the CMA by a bus.

Also, as a lower device of the CMA, a multiplexing common memory is provided, one of which, CM (1), is used as a master memory, and the other one, CM (2), is used as a slave memory, for example. Has been converted.

Then, in the common memory adapter CMA, an abnormality detection circuit AD for detecting an abnormality of the common memory CM (1) and CM (2), a flip-flop FF for switching between the master memory and the slave memory, a flip-flop FF
An inverter INV for inverting the output signal of, a control circuit, and the like are provided.

The connection between the CMA and the common memory is the same as in the conventional example described above, and the same applies to various signals.

That is, BUS is a bidirectional bus, CMDV (common valid) signal is a command valid signal sent from CMA to common memory CM, and DATV (data valid) signal is CMA.
Data valid signal sent from CM to common memory CM, DS
The END signal (data transmission signal) is a data valid signal when data is transmitted from the CM to the CMA (only the master memory can be transmitted), and the CMD is a command signal transmitted from the CMA to the CM.

Also, clock is the clock line of the common memory sent from the CMA, and the CMA and CM (1) and CM (2) are sent by the clock sent from this clock line.
Operates in synchronization.

STAT # 0 and STAT # 1 are 2-bit status signals, and END # 0 and END # 1 are end signals (end signals).

SCUT (slave cut) signal is CM (1) or CM
Of (2), it is used to disconnect the one that became the slave CM when an abnormality occurs.

MASTER and SLAVE are signals for making one of CM (1) and CM (2) a master and the other a slave, and are signals output from the flip-flop FF.

 FIG. 3 is a detailed diagram of the abnormality detection circuit of FIG.

In the figure, INV (1) to INV (4) are inverters, NAND (1) to NAND (5) are NAND circuits, respectively.
AND (1) to AND (4) are AND circuits, JK-1 to JK-1, respectively.
JK-4 is a JK flip-flop, D is a D flip-flop, MD is a master side decoder, and SD is a slave side decoder.

Also, as the input signal, 2 bits of STAT # 0 are ST
AT0 # 0 and STAT1 # 0, 2 bits of STAT # 1 are ST
AT0 # 1 and STAT1 # 1, END # 0 and END # 1 respectively
It becomes END # 0 and END # 1.

Next, the specific example shown in FIGS. 4 to 6 will be described.

(1) Reading from CM (when the master memory CM (1) is normal and the slave memory CM (2) is non-responsive (abnormal) in the sequence (see FIG. 4).

In this case, the data is read in the same manner as the above-mentioned conventional example.

In other words, data transmission and DSEND signal transmission are performed by the CM that received ON from the master signal (in this figure, the CM by MASTER
Only (1) is the master).

CMA requests read from CPU1 or CPU2 (Read request)
When it receives a message, it takes a predetermined procedure, sets the memory address (ADD) and data length (LNG) to BUS, sets the CMD signal to read (Read), and turns on the CMDV signal.

 After that, turn off the CMDV signal and wait for the DSEND signal.

When the DSEND signal is received, the data on the BUS at that time is received. In this way, when 1 byte of data is received 8 times for each system clock, the CM that is the master memory
From (1), END signal (END # 0) and status signal (ST
AT) will be sent.

However, at this time, there is no response from the slave memory CM (2) (no END # 1 signal and STAT # 1 signal).

Therefore, at this time, the abnormality detection circuit detects this, and based on this, the SCUT (slave cut) is turned on to disconnect the CM (2) which is the slave memory.

After all, if there is no response, the abnormal memory is disconnected without waiting for the timer to time out as in the conventional case.

Then, only the remaining memory executes the next cycle.

(2) Master CM in the read sequence from CM
(1) Normal, Slave CM (2) Abnormality (with response) In this case, CM (1) is normal and CM (2) is abnormal (reported). As in this example, when an abnormality occurs during data transmission and the abnormality detection circuit detects the abnormality signal (B # 11 signal of END # 1), this is ignored and the normal response of CM (1) ( Only when there is END # 0 and STAT signal), it is treated as if there was no END signal from CM (1) at that time.

Therefore, in this example, since the abnormal signal of END # 1 is ignored, SCUT becomes ON in the cycle after END # 0 is issued, and the slave memory CM (2) is disconnected.

(3) When the slave memory CM (2) is normal and the master memory CM (1) is abnormal in the read sequence from the CM In this example, the master memory CM is in the middle of data transfer.
This is a case where the abnormal signal (STATB “11”) is output from (1) but the normal end signal is output from the slave memory CM (2).

 At this time, the abnormal signal output from CM (1) is ignored.

Then, since the master memory is abnormal, the state of the flip-flop FF is inverted, the master and the slave are inverted, and the new slave memory is separated.

That is, the slave memory CM (1) is disconnected while the CM (2) is the master and the CM (1) is the slave.

The operation of the abnormality detection circuit shown in FIG. 3 is as follows.

END signal is "0" when not completed, "1" when completed normally, STAT is 2
It consists of bits, "00" is normal, "01" is 1-bit error, "10" is 2-bit error, and "11" is abnormal (up to 2-bit error is considered normal).

(1) When both master and slave are normal (Figs. 8 and 9)
(Refer to the figure) Input signals are END # 0B “1” (meaning that the END # 0 bit is “1”), STAT0 # 0 (1st bit of STAT # 0) B “0”, S
TAT1 # 0 (2nd bit of STAT # 0) B “0”, END # 1B
These are “1”, STAT0 # 1B “0”, and STAT1 # 1B “0”.

With this signal, the outputs of NAND (1) to NAND (4) all become "0", and the output of NAND (5) becomes "1".
The outputs of (1) to AND (4) are all "0".

Therefore, the decoder outputs on the master and slave sides are B
It becomes "00" and a signal indicating that it is normal is output.

(2) Both the master and slave are normal, but the master memory has a 1-bit error and the slave memory has a 2-bit error (see Figures 8 and 9). Input signals are END # 0B “1”, STAT0 # 0B “1”, STAT1 # 0
B “0”, END # 1B “1”, STAT0 # 1B “0”, and STAT1 # 1B “1”.

With this signal, the outputs of NAND (1) and NAND (4) are "1", and the outputs of NAND (2) and NAND (3) are "1".

Therefore, the output of AND (1) and AND (4) is "1" and AN
Since the outputs of D (2) and AND (3) are "0", the output of the master side decoder MD is B "01" and the output of the slave side decoder SD is B "10".

However, in this case, since there are 1-bit error and 2-bit error, they are treated as normal in this example.

(3) When the master memory is normal and the slave memory is abnormal (see Fig. 5) The input signals are END # 0B “1”, STAT0 # 0B “0”, STAT1 # 0
B “0”, END # 1B “1”, STAT0 # 1B “1”, and STAT1 # 1B “1”.

This signal causes the outputs of NAND (1) and NAND (2) to be "0" and the outputs of NAND (3) and NAND (4) to be "1",
The output of ND (5) becomes "1".

Therefore, the output of AND (1) and AND (2) is AND with "0".
Since the outputs of (3) and AND (4) are "1", the output of the master side decoder MD is B "00", which is normal, and the output of the slave side decoder SD is B "11," which is an abnormal signal.

It should be noted that, in the above embodiment, the case where one of the common memories is normal and the other is non-responsive (abnormal) has been described, but it is conceivable that both lower-level devices become non-responsive at the same time.

However, since such an abnormality is considered to be extremely rare, in that case, the time will be detected by the timer as in the conventional case.

〔The invention's effect〕

As described above, the present invention has the following effects.

Even if one of the multiplexed devices (for example, memories) has a failure such that there is no response, the disconnection operation can be performed without degrading the performance.

Further, even if the completion reports of the respective multiplexed devices come at different timings, there is no need to store the error status and the like, and there is an effect that the circuit can be simplified.

[Brief description of drawings]

 FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is an example of an abnormality detection circuit in the present invention, and FIGS. FIG. 7 is a configuration diagram of a conventional example, and FIGS. 8 to 12 are operation explanatory diagrams of the conventional example. CMA …… Common memory adapter AD …… Abnormality detection circuit FF …… Flip-flop INV …… Inverter CM (1) …… Common memory (master memory) CM (2) …… Common memory (slave memory) NAND …… NAND circuit AND …… AND circuit MD …… Master side decoder SD …… Slave side decoder JK-1 to JK-4 …… JK flip-flop D …… D flip-flop

Continuation of the front page (56) References JP-A-54-529 (JP, A) JP-A-57-125446 (JP, A) Actually developed JP-A-62-166539 (JP, U)

Claims (1)

[Claims] 1. A multiplexed lower device is provided, and these lower devices perform a synchronous operation by a clock sent from the upper device, and the lower device normally ends an execution result for a command issued from the upper device. In the case of a multiplexing device, an operation report of normal response is reported in case of abnormality, and an operation completion report of abnormality report is reported in addition to the termination status in case of abnormality detection. Means (A
D) is provided, and if there is an abnormal report that is faster than the normal response from the lower device, it is ignored and it is considered that there is no response, and a normal response to the command execution from any one of the lower devices. An abnormality detection method for a multiplexing device, characterized in that it is configured to perform control based on the execution result of this command at the time of receiving.