JPH0251298B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a frequency dividing device, particularly a 2/3 frequency dividing device, which is frequently used in digital systems.

Structure of conventional example and its problems The above-mentioned frequency dividing device is disclosed in, for example, U.S. Patent No.
No. 3967205, the structure includes a counter, an output decoder thereof, a toggle flip-flop circuit triggered by the output decoder, and a counter according to the output of the toggle flip-flop circuit. The clock signal consists of a control circuit that supplies an inverted signal or a non-inverted signal of the clock signal to the counter, and when frequency division is performed by 2/3, the number of bits of the counter is 2, and the number of gates required for the entire device is determined by the toggle frequency. Assuming that the flip-flop circuit consists of 6 gates, there are 23 gates (12 gates for the counter, 1 gate for the decoder, 6 gates for the toggle flip-flop circuit, and 4 gates for the control circuit, for a total of 23 gates). Become.

On the other hand, as is well known, the most representative 1/
The divide-by-3 device includes two D flip-flop circuits,
Since it is constituted by a combination of one logic gate, the number of required gates is 13, and compared to this, there was a problem that the number of required gates of the above-mentioned 2/3 frequency divider is considerably larger.

Purpose of the Invention The purpose of the present invention is to configure 1/3 and 2/3 frequency-divided signals of an input signal with a smaller number of logic gates in the same circuit configuration, thereby reducing power consumption and incorporating this type of device. The purpose of this technology is to make it possible to reduce the chip size of integrated circuits.

Structure of the Invention The frequency dividing device of the present invention includes a toggle flip-flop circuit that has a first output state and a second output state and inverts the output state each time a trigger signal is supplied to an input terminal. a first gate means to which the output signal of the toggle flip-flop circuit is supplied, and selects and outputs either a non-inverted signal or an inverted signal of the input clock signal according to its state; and the first gate means a first bistable circuit whose output signal is supplied to its input terminal and enters a set state;
The output signal of the first bistable circuit is supplied to the input terminal of the bistable circuit, the output signal of the first gate means is supplied to the second input terminal of the second bistable circuit, and the second bistable circuit outputs an AND output signal of both input signals. gate means of; and said second gate means.
a second bistable circuit whose input terminal is supplied with an output signal of the gate means to enter a set state; said input clock signal is supplied to said input clock signal, and third gate means is provided for supplying an AND output signal of both input signals to said toggle flip-flop circuit to invert the output of said toggle flip-flop circuit. It is configured.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a logical configuration diagram of a frequency dividing device according to an embodiment of the present invention. In the same figure,
Input/output terminal of NAND gate 1 and NAND gate 2
The input/output terminals of the NAND gate 3 and the input/output terminals of the NAND gate 4 are cross-coupled to form a bistable circuit 101, and the input/output terminals of the NAND gate 3 and the input/output terminals of the NAND gate 4 are cross-coupled to form a bistable circuit 102, Gate 5 input/output terminal and
The input and output terminals of the NAND gate 6 are cross-coupled to form a bistable circuit 103.

On the other hand, the clock signal input terminal A is connected to the input terminal of the inverter 7, and the NAND gate 5 is connected to the clock signal input terminal A.
The first and second input terminals of a NAND gate 8 are connected to the output terminal of the NAND gate 6 and the clock signal input terminal, respectively, and the output terminal of the NAND gate 6 and the output terminal of the inverter 7 are respectively connected to
The first and second input terminals of the NAND gate 9 are connected, and the output terminals of the NAND gates 8 and 9 are connected to each other.
The first and second input terminals of the NAND gate 10 are connected to each other.

Further, a second input terminal of the NAND gate 1 is connected to an output terminal of the NAND gate 10,
First and second input terminals of a NAND gate 11 are connected to the output terminal of the NAND gate 1 and the output terminal of the NAND gate 10, respectively.
The second input terminal of the NAND gate 3 is connected to the output terminal of the NAND gate 11.
The second input terminal of the NAND gate 4 is the NAND
It is connected to the output terminal of the gate 1, and the frequency division output terminal B is connected to the output terminal of the NAND gate 4.

Furthermore, the input and output terminals of NAND gate 12 and
The input and output terminals of the NAND gate 13 are cross-coupled to form a bistable circuit 104.
A second input terminal of the NAND gate 12 is connected to the second input terminal of the NAND gate 12.
connected to the output terminal of NAND gate 3, and
The second input terminal of the NAND gate 13 is
connected to the output terminal of the NAND gate 10;
The output terminal of the NAND gate 12 is connected to the second input terminal of the NAND gate 2, and the output terminal of the NAND gate 1 is connected to the second input terminal of the NAND gate 2.
0 and the input terminal of the inverter 14 are connected. A NAND gate 16 and a NAND gate 1 are connected to the output terminal of the inverter 14.
The first input terminal of the NAND gate 16 is connected to the clock signal input terminal A, and the second input terminal of the NAND gate 16 is connected to the clock signal input terminal A.
The second input terminal of the NAND gate 5 and the NAND
A fourth input terminal of the gate 10 is connected to the
The second input terminal of the NAND gate 17 is connected to the output terminal of the inverter 7, and the second input terminal of the NAND gate 6 and the
A fifth input terminal of NAND gate 10 is connected.

Regarding the frequency dividing device configured as above, the second
The operation will be explained based on the time chart shown in the figure.

In Fig. 2, AX is the signal waveform supplied to the clock signal input terminal A, 7X, 16X,
17X, 5X, 6X, 8X, 9X, 10X, 13
X, 12X, 1X, 2X, 11X, 3X, 4X,
14X are inverter 7, NAND gates 16, 17, 5, 6, 8, 9, 10, 13, 1, respectively.
2, 1, 2, 11, 3, 4 are the output signal waveforms of the inverter 14.

In advance, with the level of the clock signal input terminal A being "L" and the output levels of NAND gates 1, 3, and 5 also being "L", the leading edge of the clock signal AX arrives at time _t1 . Then, if the level shifts to “H”,
Subsequently, the output level of the inverter 7 shifts to "L", and further the output level of the NAND gate 9 shifts to "H".
, and the output level of the NAND gate 10 shifts to "L".

“L” output level of the NAND gate 10
By migrating to NAND gate 13 and
The output level of NAND gate 1 shifts to “H”,
As the output level of the NAND gate 1 shifts to "H", the output level of the NAND gate 2 shifts to "L". (The bistable circuit 101 is set.) At this time, since the output level of the NAND gate 3 is maintained at "L", the output level of the NAND gate 13 shifts to "H".
The output level of the NAND gate 12 never shifts to "L".

When the trailing edge of the clock signal arrives at time _t2 , the output level of the inverter 7 shifts to "H", then the output level of the NAND gate 9 shifts to "L", and the output level of the NAND gate 10 shifts to "H".
The output level shifts to "H".

“H” output level of the NAND gate 10
As a result of the transition to , the output level of the NAND gate 13 shifts to "L", and the output level of the NAND gate 11 shifts to "L", and then
The output level of NAND gate 3 shifts to “H”,
As a result, the output level of NAND gate 4 is “L”
to move to. ( _The bistable circuit 102 is set.) When the leading edge of the clock signal arrives at time _t3 , the inverter 7, NAND gate 9, NAND gate 10,
The output level of the NAND gate 13 changes, and the
As the output level of the NAND gate 10 shifts to "L", the output level of the NAND gate 11 shifts to "H".

In addition, since the output level of the NAND gate 3 has already become "H", the NAND gate 13
By shifting the output level of NAND to “H”
The output level of the gate 12 shifts to "L", and as a result, the output level of the NAND gate 10 returns to "H", and at the same time, the output level of the NAND gate 2 shifts to "H".

As the output level of the NAND gate 2 shifts to "H", the output level of the NAND gate 1 shifts to "L", and then the output level of the NAND gate 4 shifts to "H", and as a result, The output level of NAND gate 3 shifts to "L".

As the output level of the NAND gate 3 shifts to "L", the output level of the NAND gate 12 returns to "H", and subsequently the output level of the NAND gate 13 returns to "L".

On the other hand, when the output level of the NAND gate 12 shifts to "L", the output level of the inverter 14 shifts to "H", and as a result, the output level of the NAND gate 16 shifts to "L", and then
The output level of NAND gate 5 shifts to "H".

As the output level of the NAND gate 5 shifts to "H", the output levels of the NAND gates 6 and 8 shift to "L".

Note that the output level of the NAND gate 16 returns to "H" after the output level of the NAND gate 12 returns to "H", and then the output level of the inverter 14 returns to "L".

When the trailing edge of the clock signal arrives at time _t4 , the inverter 7 and
The output level of NAND gate 8 shifts to "H",
Next, the output level of NAND gate 10 becomes “L”
to move to.

The output level of the NAND gate 10 is “L”
, the output levels of NAND gate 13, NAND gate 1, and NAND gate 2 change as at time _t1 .

At time _t5 , when the leading edge of the clock signal arrives, the output levels of inverter 7 and NAND gate 8 shift to "L", and then
The output level of the NAND gate 10 shifts to "H".

The output level of the NAND gate 10 is “H”
, the output levels of NAND gate 13, NAND gate 11, NAND gate 3, and NAND gate 4 change as at time _t2 .

At time _t6 , when the trailing edge of the clock signal arrives, inverter 7, NAND gate 8, NAND gate 10, and NAND gate 13
The output level changes in the same way as at time _t4 .

When the output level of the NAND gate 13 changes and shifts to "H", since the output level of the NAND gate 3 has already become "H",
The output level of the NAND gate 12 shifts to "L", and due to the change in the output level of the NAND gate 12, the NAND gate 10, NAND gate ₂ , NAND gate 1,
NAND gate 11, NAND gate 4, NAND
Gate 3, NAND gate 12, NAND gate 1
3. The output level of the inverter 14 changes, and as the output level of the inverter 14 shifts to "H", the output level of the NAND gate 17 becomes "L"
to move to.

The output level of the NAND gate 17 is “L”
, the output level of NAND gate 6 shifts to “H”, and then NAND gate 5 and
The output level of NAND gate 9 shifts to "L".

When the leading edge of the clock signal arrives at time _t7 , the output level of each logic gate changes in the same way as at time _t1 , and when the trailing edge of the clock signal arrives at time _t8 , the output level of each logic gate changes. The level changes in the same way as at time _t2 .

Thereafter, the same operation is repeated every time the leading edge or trailing edge of the clock signal arrives, and an output signal whose frequency is divided by 2/3 as shown at 4X in FIG. 2 appears at the frequency-divided output terminal B.

Now, the frequency divider shown in Figure 1 is composed of 14 logic gates and has an extremely simple configuration, and as can be seen from Figure 2, the frequency can be divided by 1/3 as needed. It is also possible to extract the output signal.

By the way, the frequency dividing device of the present invention is not limited to the embodiment shown in FIG. 1, and various changes can be made as necessary. For example, FIG. 3 shows a logical configuration diagram of another embodiment of the present invention, and in FIG. 3, parts having the same functions as in FIG. 1 are given the same reference numerals.

FIG. 4 is a time chart showing the output waveforms of each logic gate and toggle flip-flop circuit 100 in FIG. 3 in the same manner as FIG.
As is clear from a comparison between the figure and FIG. 4, its operation is almost the same as that of the device shown in FIG. 1, so a detailed explanation will be omitted.

In FIG. 1, the first bistable circuit 103 and
The NAND gates 16 and 17 have a first output state and a second output state, and are toggles that invert the output state each time a trigger signal (signal waveform 14X in FIG. 2) is supplied via the inverter 14. The toggle flip-flop circuit 100 shown in FIG. 3 also has the same function. Furthermore, EX-OR gate 2 in Figure 3
00 has the same function as the gate circuit made up of NAND gates 8, 9, and 10 in FIG.

The frequency dividing device of FIG. 3 can also be constructed with fewer logic gates than conventional ones.

Effects of the Invention As is clear from the above description, the frequency dividing device of the present invention has a first output state and a second output state, and inverts the output state each time a trigger signal is supplied to the input terminal. A toggle flip-flop circuit (a circuit consisting of a bistable circuit 103 and NAND gates 16 and 17 or a toggle flip-flop circuit 1)
00) and the output signal of the toggle flip-flop circuit, the first gate means (see FIG. In the embodiment, it is composed of NAND gates 8, 9, and 10,
In the embodiment shown in FIG. 3, the EX-OR gate 200 and
It is composed of a NAND gate 15. ), and a first bistable circuit 101 which enters a set state when the output signal of the first gate means is supplied to the input terminal.
The output signal of the first bistable circuit is supplied to a first input terminal, the output signal of the first gate means is supplied to a second input terminal, and an AND output signal of both input signals is supplied. a second gate means (consisting of a NAND gate 11) for outputting;
a second bistable circuit 10 which enters a set state when the output signal of the second gate means is supplied to the input terminal;
2, an output signal of the second bistable circuit is supplied to a first input terminal, an input clock signal is supplied to a second input terminal, and an AND output signal of both input signals is supplied to the toggle flip-flop circuit. and a third gate means (consisting of a NAND gate 12) for inverting the output of the toggle flip-flop circuit by supplying the gate means to the toggle flip-flop circuit. By extracting the output signal of the bistable circuit, it is possible to obtain a frequency divider that divides the frequency of the input clock signal by two-thirds with a smaller number of logic gates than in the past. By taking out the output signal of the circuit, it is possible to obtain a frequency dividing device that divides the frequency of the input clock signal by one-third with the same circuit configuration, which brings about great effects.

[Brief explanation of drawings]

FIG. 1 is a logical configuration diagram of a frequency dividing device according to an embodiment of the present invention, FIG. 2 is a time chart for explaining its operation, and FIG. 3 is a logical configuration diagram of another embodiment of the present invention. FIG. 4 is a time chart for explaining the operation. 100...Toggle flip-flop circuit, 10
1... Bistable circuit, 102... Bistable circuit, 10
3... Bistable circuit.

Claims (1)

[Claims] 1 A toggle flip-flop circuit having a first output state and a second output state and inverting the output state each time a trigger signal is supplied to an input terminal, and an output signal of the toggle flip-flop circuit. is supplied, and a first gate means selects and outputs either a non-inverted signal or an inverted signal of the input clock signal according to the state thereof, and an output signal of the first gate means is supplied to an input terminal. a first bistable circuit that is in a set state; a first input terminal is supplied with an output signal of the first bistable circuit; and a second input terminal is supplied with an output signal of the first gate means; , a second gate means for outputting an AND output signal of both input signals, a second bistable circuit whose input terminal is supplied with the output signal of the second gate means to be in a set state, and a first bistable circuit. An output signal of the second bistable circuit is supplied to an input terminal, a second input terminal is supplied with the input clock signal, and an AND output signal of both input signals is supplied to the toggle flip-flop circuit. and third gate means for inverting the output of the toggle flip-flop circuit, the output signal of the second bistable circuit being a two-thirds divided output signal of the input clock signal, or A frequency dividing device which extracts the output signal of the toggle flip-flop circuit as an output signal divided by one third of the input clock signal.