JPH0251738A - Automatic translation method from digital circuit data to logic simulation description language - Google Patents

Abstract

PURPOSE:To improve the working efficiency of the logical simulation and to simplify a translation program by preparing a function to translate each logical function into a logical simulation describing language while interpreting an editing command table. CONSTITUTION:An editing command table is produced for all logical functions to be used to a digital circuit and stored in an editing command table file 202. Then one of logical functions of the digital circuit is read out of a circuit data file 201. Then it is checked whether the circuit data is through or not. In case the circuit data is not through and is still read, the editing command table corresponding to the read logical function is read out of the file 202. Then the read circuit data is translated into a logical simulation describing language based on the editing command table. The result of translation is stored in a logical simulation describing language file 203 as the basic information on the logical simulation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of translating digital circuit data into a logic simulation model description language.

[Conventional technology]

Conventionally, when translating digital circuit data into a logic simulation description language, the logic and functions of the digital circuit were treated as a black box, and only the connection relationships were extracted and translated into a specific language format.

[Problem that the invention seeks to solve]

The conventional method described above has the drawback that it is difficult to understand what kind of logic is included even when looking at the translated description, and the efficiency of logic simulation is poor.

[Means for solving problems]

The automatic translation system of the present invention has an editing command table that can use intermediate variables, which is necessary to express individual logical functions in a logical simulation description language, and a function that interprets this table and translates it into a logical simulation description language. are doing.

In addition, the logic function has a side path that allows additions and replacements of circuit diagram data and editing command tables to be freely changed from the outside.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a process flow diagram showing an embodiment of the automatic translation method of the present invention. Edit command table of 201 and 202
The circuit data 203 and the logic simulation description language 203 are saved as files. The program that specifically implements this processing flow as a function is FORTRAN.
It is written with a compiler such as

FIG. 2 is a block diagram showing the configuration of an automatic translation system when this program is implemented on an ordinary computer. The three files 20], 202, and 203 shown in FIG. 1 are stored on the magnetic disk 4. The circuit data is created, for example, on a CAE (Computer Aided Engineering) workstation implemented on a personal computer, and the command table is obtained by inputting it into the host computer 3 from the keyboard 2. keyboard 2
Its role is to input translation programs and give execution instructions to the host computer 3. Note that the program is loaded onto the main memory of the host computer 3 and operates.

Next, the operation of the present invention will be explained with reference to FIG.

First, in step 101, an edit command table (described later) is created for all logical functions scheduled to be used in the digital circuit, and is stored in the edit command table file 202. Note that it is desirable to create this editing command table file 202 in advance. Next, in step 102, a circuit data file 201 (circuit data will be described later)
reads one of the logic functions of the digital circuit. In step 103, it is checked whether there is any unprocessed data among the circuit data, that is, whether the circuit data is finished. If the circuit data is not finished but has been read, in step 104, the editing command table corresponding to the read logic function is saved to file 2.
Read from 02. Next, in step 105, the read circuit data is translated into a logic simulation description language (described later) according to the editing command table,
The results are stored in the logic simulation description language file 203 and used as basic information for the logic simulation.

FIG. 3 is a circuit diagram showing an example of a digital circuit obtained by inputting data into the CAE workstation of the personal computer 1 shown in FIG. 10 is a decoder, 11 is input data to line name A#, the signal name is "PRBO (0-2)", and it has a size of 3 bits. 12 is the control line to line name EI, the signal name is rAOO6[YJ, 13 is the output data from line name Y#, and 5 is the signal name rDEco (0-
7) J's is 8bi soto. The magnetic disk file 4 is stored on the host computer 3 in the format shown in FIG.
have it as a digital circuit data file. In this example, the part corresponding to the decoder 10 (row A on the data,
(shown in line B) are shown. A row 42; 24
and 3E;25... in line B indicate the coordinate values on the circuit drawing, A005 indicates the part number, ``DEC#'' indicates the logical function name, and °' A O'' to `` in line B Y7" is a line name unique to the logical function, ""PRBO(0)" to "D"
"ECO(7)" is a signal name indicating that the same potential exists between logic functions.L indicates an input signal to the logic function, and S indicates an output signal.This circuit data is predefined for each logic function. It is summarized in

FIG. 5 is a diagram showing an example of the format of an editing command table for translating digital circuit data into a logic simulation description language.

FIG. 6 is a diagram showing examples of symbols input into the forma-soto of FIG. 5 and their meanings. In each column of the format shown in Figure 5, as shown in Figure 6, the name of the logical function required as a table, the function type, the number of lines indicating whether the definition of intermediate variables is represented as bait, and the editing command. The number of rows to store and other necessary definition statements are entered for each row, and it is configured to function as a table.

FIG. 7 is a diagram showing an example of an editing command table for the decoder section for translating the circuit diagram data of the decoder section shown in FIG. 4 into a logic simulation description language. "rDEc#" is entered in the 5CODE column as the logical function name, and rsMAc is entered in the FTYPE column as the function type.
J is entered in the RNO1 column as the number of definition lines of the intermediate language (since there is no definition content in this example), and "0" is entered in the RNO2 column as the number of lines in which the editing command is stored.

From the next line onward, the edit command is stored over four lines since line "4" is entered in the RNO2 column of the first line. In other words, on the second line there is a line break mark of “1
” is shown, and to the right is “2” as the column position, rTERMINALJ as the text 1, followed by r6j as the column position, and the logical function-specific line name (in this example, the output of the decoder) as the LPIN “Y#”. However, the content as text is also stored. The specific command is input and stored after the next line. 'A#J and 'Y#'
represent rAo to A2J and rYo to Y7J in FIG. rEIJ is the same as "E■" in FIG.

Figure 8 is a diagram showing an example of translating the digital circuit data in Figure 4 into a logic simulation description language.
This shows the results of translation according to the editing command table in the figure. The language used here is Behavior Disclosure (Behavior Dtsc).
ription) type.

FIG. 9 is a circuit diagram showing an example of a sequence controller as a second example of translation. When this sequence controller is translated according to the editing command table shown in FIG. 10, the translation result shown in FIG. 11 is obtained. Intermediate variables #REG, #SP, #RAM, #TN
C each has a unique signal name 5OIL, 5O12, 5O
1B, 5014. In order to simplify the explanation, the line names and signal names specific to the logical functions are the same.

〔Effect of the invention〕

As explained above, in the present invention, each logical function can be expressed in a logical simulation description language, so that the efficiency of logical simulation is improved. Also, since the editing command table is used, the translation program becomes simpler and the execution speed is faster.

○ Intermediate variables can be used, so logical functions that have multiple levels of internal memory can be easily understood and translated.

0 logic functions can be added and replaced freely, making maintenance and operation easy.

The effects are enormous.

[Brief explanation of the drawing]

FIG. 1 is a processing flow diagram showing an embodiment of the present invention, FIG. 2 is a system block diagram implementing the present invention, and FIG. 3 is a circuit diagram showing an example of a first digital circuit translated by the present invention.
Fig. 4 is a diagram showing circuit data of the decoder part of Fig. 3;
Figure 5 is a diagram showing the format of the editing command table, Figure 6 is a diagram showing examples of symbols input into the format of Figure 5 and their meanings, and Figure 7 is the circuit diagram shown in Figure 4. A diagram showing an example of an editing command table for translating data, FIG. 8 is a diagram showing the translation result of the data shown in FIG. 4, and FIG. 9 is a diagram showing an example of the second digital circuit translated by the present invention. FIG. 10 is a diagram showing an example of an editing command table corresponding to the circuit diagram of FIG. 9, and FIG. 11 is a diagram showing a translation result. 1 is a personal computer, 2 is a keyboard, 3 is a host computer, 4... magnetic disk files, 101 to 105 are processing steps, and 201 to 203 are files, respectively.

Claims (1)

[Claims] Logic simulation description language is created by extracting logical connection information from the graphic data of a digital circuit and using the logical function name included in the logical connection information as a key word according to an editing command table in which the meaning of each figure is set in advance. A method for automatically translating digital circuit data into a logic simulation description language.