JPH025295A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the glitch of an output waveform and to realize a multi-bit constitution of a semiconductor device while satisfying a high-speed data processing request by dropping immediately the base potential of an R/W transistor in the latter writing period. CONSTITUTION:A writing circuit 50 consists of transistors TR 51-56, resistance 57-59, current sources 60-61, a delay circuit 62, and an inverter 63. An output signal set at a high level is reset at the potential set at reading and supplied to the control (R/W) TR 51 and 52 inserted into a pair of bit lines out of those output signals of the circuit 50 set at high levels in the prescribed timing before the end of a writing action. Therefore both TR 51 and 52 are never turned off temporarily when the writing action is through. Thus it is possible to obtain a semiconductor memory of a multi-bit constitution that can prevent the output glitch after a writing action while maintaining the high-speed data processing performance.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 5 to 7) Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems (1) Sections of the Invention 1st embodiment (Fig. 1.2) (2) 2nd embodiment of the present invention (Fig. 3) (3) 3rd embodiment of the present invention (Fig. 4) Effects of the invention [Summary] Concerning a semiconductor memory device The purpose is to provide a semiconductor memory device with a multi-bit configuration that can prevent output gridlock after the end of a write operation while maintaining high-speed data processing. A large number of bipolar memory cells are arranged in a grid, and a control transistor for controlling data writing/reading is inserted in each bit line, and the control transistor is connected to the memory cell when writing data to the memory cell. It controls the potential of the selected bit line pair, and when writing data,
In a semiconductor memory device in which a predetermined write circuit sets the input level of the control transistor to a high level and the other to a low level compared to a potential at the time of reading, the write circuit sets The one input level set to the high level is returned to the read potential at a predetermined timing.

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that is applied to a bipolar RAM and has an improved write circuit.

Because bipolar RAM operates at high speed, it is used as a buffer device in large computers, but in recent years it has become faster and faster.
Larger capacity is required. For this reason, miniaturization of elements is progressing using the latest lithography technology, and countermeasures are also being taken in terms of circuitry, such as mounting a RAM and a peripheral logic section on the same chip. Furthermore, in order to speed up the system, it is necessary to process a large amount of data at once, so it is also necessary to increase the memory configuration to a multi-bit configuration.

[Conventional technology]

As a conventional bipolar RAM, one shown in FIG. 5, for example, is known. Figure 5 shows bipolar RAM
1 is a circuit diagram showing the periphery of a cell, and in this figure, 1
a, 1b, 2a12b are word lines, 3a, 3b, 4a,
4b is a bit line.

Although a large number of such word line pairs and bit line pairs are provided, FIG. 5 shows two pairs each.

Word lines 1a, ■b, 2a, 2b and bit lines 3a,
Memory cells 5 to 8 are arranged in the lattice-shaped portion defined by 3b, 4a, and 4b, and the circuit for only one memory cell 5 is shown. The memory cell 5 is called a diode clamp type multi-emitter memory cell, which is currently the mainstream, and is composed of a transistor 9.10, a Schottky barrier diode 11.12, and a resistor 13.14. The memory cell 5 is selected or unselected in the row direction depending on the potential of the word line 1a, and is set to a level such that, for example, it is selected at -0, 8V, and unselected at -1, 7V.

On the other hand, selection in the column direction is performed when a bit line selection signal B1 is applied to the base of transistor 15.16, which causes current source 17.18 to select bit vA3 a .

3b, respectively. In addition, the current sources 17.18 are connected to the power supply v□, Vtt=5.2 V, GND
=0■. Similarly, transistors 19 and 20 are inserted in unselected bit lines 4a and 4b, so that a bit line selection signal B2 can be applied.

When reading, the write circuit 21 outputs an intermediate level (for example, -1).
, 2V corresponds to the potential during readout) is R/W)
Run lister (transistor for read/write control) 2
2.23 applied to the base. Now, when the transistor 10 of the memory cell 5 is on and the transistor 9 is off, the transistor 10 and the R/W) run lister 22 and the transistor 9 and the R/W) run lister 23 constitute an ECL circuit, and the base potential Since the current flows through the transistor with the highest current, the current source current IR due to the current al
It flows from 3. Detection of the memory contents of the transistor 15 is performed based on the potential drop of the resistors 24 and 25. That is, in the above example where the transistor 10 is on and the transistor 9 is off, no potential drop occurs in the resistor 24, but a potential drop with a resistance value of XIIIW' occurs in the resistor 25. This voltage is applied to the sense amplifier 26
is amplified and taken out as read data.

Next, during writing, the base potential of one R/Wl-run lister 22 is moved from an intermediate level to a high level, and the base potential of the other R/Wl-run lister 22 is moved from an intermediate level to a high level.
A write operation is possible by setting the base potential of the /W transistor 23 to a low level.

With this setting, the base potential of the transistor 90 becomes higher than that of the R/W) run lister 23, so the current source current 1+iw flowing through the R/W transistor 23 is switched to the transistor 9. Therefore, the collector potential of transistor 9 is lowered, and transistor 10 changes from on to off. After that, R/Wl-Run Lister 2
Even if the base potential of 2.23 is returned to the read level (intermediate level), the new information is retained and the write operation is completed, since the base collector of transistor 9.10 is cross-connected. Note that the same operation is performed for the memory cells 6, 8, etc. connected to the other bit lines 4a, 4b, and the R/W) run list 2 is connected to the bit lines 4i14a, 4b.
7.28 are inserted respectively.

Here, when considering a 256 bit l-RAM as a unit, the X:Y(7) ratio is 16X16.
When it is 256×4, it becomes 32×8.256×8 or more, it becomes 64×4. In this case, the emitters of memory cells as many as X are connected to the bit line, and the load on the R/Wl-run lister increases as the number of bits increases. On the other hand, the output of the write circuit 21 is R/W
Since the base of the L-run lister becomes a load, the load becomes smaller as the number of bits increases.

FIG. 6 is a diagram showing an example of the write circuit 21. In this figure, the write circuit 21 is composed of transistors 31 to 37, current sources 38 to 41, and resistors 42 to 44, and the potential levels of the signals W, D, D, and Vref used are the seventh.
It is as shown in figure (a).

When the write enable signal W is set to W-“H” during reading, only the transistor 35 is turned on among the three transistors 33 to 35 whose emitters are commonly connected, and the current from the current source 40 is transferred from the resistor 42 to the transistor. Current from current source 41 flows through transistor 36 while flowing through transistor 35 . Therefore, no potential drop occurs in the resistors 43 and 44, and therefore, potentials at the same level (corresponding to an intermediate level) are taken out as two outputs via the emifter lock transistors 31 and 32, respectively, and the R/W are supplied to transistors 22 and 23, respectively. At this time, the output waveform of the write circuit 21 is shown as shown in FIG. 7(b), and is at an intermediate level.

On the other hand, during writing, a level corresponding to predetermined data is added to the data signal D, and W="L" is set. Therefore, whichever of the transistors 33 and 34 is turned on according to the write data signals D and D. For example, in Figure 7 (a
), when D is at a low level and D is at a high level, the transistor 34 is on, the transistor 33 is off, and the current from the current source 40 flows through the transistor 34 via the resistor 42 and the resistor 44. On the other hand, since the transistor 37 is turned on, the current from the current source 41 flows through the transistor 37. Therefore, resistance 43.4
A potential difference is created between transistors 3 and 4, which causes a potential difference between transistors 3 and
1.32, and its output level is shown as shown in FIG. The output signal has a low level (for example, -1, 8V) with respect to an intermediate level (-1, 2V).

Then, the output signals having different levels as described above are applied to the bases of the R/W transistors 22 and 23 shown in FIG. 5, and the write operation described above is performed.

[Problem to be solved by the invention]

However, in such a conventional bipolar RAM, when the output level of the write circuit returns from the write level to the read level (intermediate level), the memory cell has a multi-bit configuration (for example, when X:Y=64X4). ), the number of loads attached to the output side of the write circuit is four, but the R/W
The number of loads attached to the emitter side of one transistor is 64, and the loads on both sides become unbalanced. For this reason, the emitter potential decreases more slowly than the base potential of the R/W transistor, and the R/W transistor is cut off and the collector current decreases. In this case, since the output of the RAM detects the collector current of this R/Wl-run lister, there is a problem that a glitch occurs in the output waveform by the time width of the cutoff.

Here, a glitch is a protruding so-called whisker in the output waveform, which exceeds a threshold level and becomes noise. For example, even though the output is originally "L", it temporarily A problem arises in that the logic of "1■" appears in .

Note that even if it is a multi-bit configuration, for example, 64 x 64
If the cell arrangement is close to a so-called square where X:Y is equal as shown in the figure, the reload imbalance described above will not occur.
This does not lead to the occurrence of glitches. Therefore, when the cells are arranged in a rectangular manner, the glitch problem becomes more noticeable. In order to solve this problem, for example, it may be possible to lengthen the data processing time (cycle time), but this would go against the recent demands for high speed.
Not valid.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-bit semiconductor memory device that can prevent output glitches after the end of a write operation while maintaining high-speed data processing.

[Means to solve the problem]

In order to achieve the above object, a semiconductor memory device according to the present invention has a large number of bipolar memory cells selectable by word lines and bit lines arranged in a grid, and a control transistor for controlling data writing/reading on each bit line. is inserted, and the control transistor controls the potential of a selected bit line pair connected to the memory cell when writing data to the memory cell, and when writing data, the control transistor controls the potential of a selected bit line pair connected to the memory cell. In a semiconductor memory device in which a circuit sets the input level of the control transistor to a high level and the other to a low level compared to a potential at the time of reading, the write circuit controls the input level of the control transistor at a predetermined timing before the end of the write operation. It is configured to return one of the human power levels set to the high level to the potential at the time of reading.

[Effect]

In the present invention, at a predetermined timing before the end of the write operation, one of the output signals of the write circuit set to a high level is returned to the read potential, and the control transistor (R /W transistor).

Therefore, the R/W transistor does not temporarily turn off at the end of the write operation, and glitches in the data output waveform are effectively prevented.

〔Example〕

-Hereinafter, the present invention will be explained based on the drawings.

FIG. 1.2 is a diagram showing one embodiment of a semiconductor memory device according to the present invention. Although the present invention is applied to a bipolar RAM, among the RAM peripheral circuits, this embodiment has a feature in the write circuit, so the write circuit will be fully disclosed, and the other configurations are shown in FIG. Since this is the same as the conventional example, it will be omitted.

FIG. 1 is a circuit diagram showing a write circuit applied to a bipolar RAM. In this figure, a write circuit 50 includes transistors 51 to 56, resistors 57 to 59, current sources 60 to 61
, a delay circuit 62 and an inverter 63. The bases of transistors 51 and 52 receive data signals,
D is supplied to each, and the emitters of transistors 51 to 53 are commonly connected to form an ECL circuit and a current source 6
0, and the output is taken out from each collector side of the transistors 51 and 52. Furthermore, the emitters of transistors 54 to 56 are similarly connected in common to form an ECL circuit and are connected to a current source 61, and a write enable signal W is applied to the bases of transistors 53 and 54.
A reference voltage Vre is supplied to the base of the transistor 56, and a write enable signal W is supplied to the base of the transistor 56 via a delay circuit 62 and an inverter 63.The delay circuit 62 delays the write enable signal W by a predetermined time. The delay time is set in advance to an appropriate value (a value that does not cause glitches), and this can be determined through experiments, etc. The potential relationship of each signal, D, W, and Vref, is This is similar to that shown in FIG. 7(a).

In this embodiment, the collector currents of the transistors 51 and 52 are taken out as output as they are, but a one-stage emitter-follower amplifier may be inserted after this as in the conventional example to take them out to the outside.

In the above configuration, when the write enable signal W is set to "H" at the time of reading, the transistor 53 is turned on, and the current (2) from the current source 60 passes only through the transistor 53, and the transistors 51 and 52 which are in the off state are turned on. Since no potential drop occurs at the resistors 58 and 59, the output level is output as an intermediate level as in the conventional example. At the same time, W=“H” causes the transistor 54 to
turns on and the current I2 from the current source 61 flows through the transistor 5.
flows through 4. As a result, the resistor 57 has Il +
A current I2 will flow. Note that since the base of the transistor 56 is supplied with the W-"L" signal via the inverter 63, the transistor 56 is off. Therefore, data is subsequently read from the memory cell in the same manner as in the conventional example.

Next, when the write enable signal W is set to W-L'' during writing, the transistor 53 is immediately turned off, and one of the transistors 51 and 52 is turned on according to the level of the data signal D.

For example, if D is low level and D is high level,
The transistor 52 is turned on, the transistor 51 is turned off, and the current 1. flows through the transistor 52 via the resistor 57 and the resistor 59. At this time, W=
11" at the base of the transistor 56 for a predetermined delay time determined by the delay circuit 62 immediately after it becomes "L".
Since no level is applied, only the transistor 55 is turned on and the current I2 of the current source 61 is connected to GND (ground).
flows through the resistor 57 and does not pass through the resistor 57. Therefore, the initial stage of the write operation (the period from the start of writing to the delay time).Hereinafter,
(referred to as the initial stage of writing), only current 2 flows through the resistor 57, and its voltage drop is 1, XR.

However, R1 is the resistance value of the resistor 57. As a result, as shown in the output waveform of the write circuit 50 in FIG. 2, one output voltage becomes a high level higher than the intermediate level by the values I, XR, at the initial stage of writing, and the other output voltage is at a low level.

Next, when the delay time has elapsed (hereinafter referred to as the late write period), the write enable signal W is inverted by the inverter 63 and applied to the base of the transistor 56 in the state of W="H". At this time, since the relationship "H"> Vref exists, the transistor 56 turns on at the same time as the transistor 55 turns off, and the current I2 flows through the resistor 57, and the voltage drop across the resistor 57 is (1, +I,)xR
, becomes. Therefore, the voltage drop across the resistor 57 is similar to that during reading, and only one output voltage drops to an intermediate level (reading level) as shown in FIG. After that, when the write enable signal W returns to the "H" level, both output signals become the intermediate level again.

From the above, in this example, if the cell arrangement is X:
Even in a rectangular multi-bit configuration such as Y=64×4, the base potential of the R/W transistor is immediately lowered in the latter half of the write operation, so the R/W transistor is turned off at the end of the write operation. This effectively prevents glitches in the output waveform. Therefore, there is no need to lengthen the cycle time, and it is possible to meet the demand for multi-bit data processing while satisfying the demand for high-speed data processing.

FIG. 3 is a diagram showing a second embodiment of the semiconductor memory device according to the present invention, and shows a write circuit 70. In FIG.

In FIG. 3, the write circuit 70 includes transistors 71 to 7.
6, Resistance 77-80, Current source 81.82, Diode 8
3.84, a delay circuit 85 and an inverter 86, and each signal similar to the first embodiment is supplied to the positions shown. When W becomes "L" during writing, at the beginning of writing, ]-Langistav 5 is turned off and 1-Langistav 4 is turned off.
．． 76 is turned on and off according to the data signal D, and a current I from a current source 82 flows.

At this time, the transistor 73 is turned off and the transistor 71 is turned on at the same time, and the current I2 from the current source 81 is l.
Flows through Landistav 1. Therefore, the current caused by turning on the transistor 74 or the transistor 75 is
Current 1 flows through resistor 78 or resistor 79, but current 2 does not flow through these resistors 78 and 79. Next, in the latter half of writing, an "H" level signal is output from the inverter 86 and applied to the base of the transistor 72.
Current ■2 will flow through transistor 72, and at this time, current ■2 will flow through resistor 78 and diode 83.
The current flows through two routes, one through the resistor 79 and the diode 84. Therefore, as in the case of the first embodiment, the current flowing through the resistor 78 or the resistor 79 is limited to either the transistor 74 or the transistor 7.
5, which corresponds to the one in the on state) is (II
+12), resulting in a waveform similar to that shown in FIG. As a result, the same effects as in the first embodiment can be obtained.

FIG. 4 is a diagram showing a third embodiment of the semiconductor memory device according to the present invention, and shows a write circuit 90. In FIG.

In the write circuit 90 shown in FIG. 4, components that are the same as those of the circuit elements shown in FIG. 1 are designated by the same numbers, and parts with different arrangement or the like are designated by new numbers for explanation. The write circuit 90 includes transistors 91 and 92 as different parts.
, diodes 93 and 94, a current source 95, a delay circuit 96, and an inverter 97, and each signal similar to the first embodiment is supplied to the positions shown. W=“ at the beginning of writing
When it becomes "L", the transistor 53 is turned off and the data signal is turned on, and according to the level of D, one of the 1-run listers 51 and 52 is turned on and the current 11 flows through the resistor 57.At this time, the 1-run lister 55 is turned on at the same time. A current I2 flows. Also, the transistor 91 is connected to the delay circuit 96.
Therefore, the transistor 92 is not turned on immediately, and the current I from the current source 95 flows while the transistor 92 is turned on.

Next, in the latter half of writing, the output of the delay circuit 96 becomes “H”.
'', transistor 91 is turned on, transistor 9
2 is turned off, and current 3 begins to flow through transistor 91. Therefore, the potential of the higher one of the transistors 51 and 52 comes to exit from the transistor 91 via the diode 93 or 94, and as a result, the current I flows through the resistor 57 and is added to becomes. Therefore, the output waveform of the write circuit 90 is similar to that shown in FIG. 2, and the same effects as in the previous embodiment can be obtained.

〔effect〕

According to the present invention, it is possible to prevent output glyphage after the write operation is completed without increasing the cycle time, and it is possible to obtain a multi-bit bipolar RAM while maintaining high speed data processing.

[Brief explanation of the drawing]

1.2 is a diagram showing a first embodiment of a semiconductor memory device according to the present invention, FIG. 1 is a circuit diagram of a write circuit thereof, FIG. 2 is a diagram showing an output waveform of the write circuit, FIG. 3 is a circuit diagram of a write circuit showing a second embodiment of a semiconductor memory device according to the present invention, and FIG. 4 is a circuit diagram of a write circuit showing a third embodiment of a semiconductor memory device according to the present invention. Figures 5 to 7 are diagrams showing a conventional bipolar RAM. Figure 5 is a circuit diagram of its main parts, Figure 6 is a circuit diagram of its write circuit, and Figures 7 (a) and (b) are FIG. 3 is a signal waveform diagram illustrating the operation of the write circuit. la, lb, 2a, 2b---word line,
3 as 3 bx 4 a14 b""...Bit line, 5 to 8...Memory cell, 21...Write circuit, 22.23.27.28... R/W transistor (control transistor), 50.70.90...Write circuit, 51-56.
71-76.91-92...transistor, 5
7-59.77-80...Resistance, 60.61.
81.82.95...Current source, 62.85.9
6...Delay circuit, 63.86.97...
・Inverter. 1st v) The second part of the harm circuit of j4j is also the form Σ shown 7th prisoner Figure 2
Figure 7

Claims (1)

[Scope of Claims] A large number of bipolar memory cells selectable by word lines and bit lines are arranged in a grid, and a control transistor for controlling data writing/reading is inserted in each bit line, and the control transistor controls the potential of a selected bit line pair connected to a memory cell when writing data to the memory cell, and when writing data, the input of the control transistor is controlled by a predetermined write circuit. In a semiconductor memory device in which one level is set to a high level and the other level is set to a low level compared to a potential at the time of reading, the write circuit is set to the high level at a predetermined timing before the end of a write operation. A semiconductor memory device characterized in that it is configured to return one input level to a read potential.