JPH025529A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH025529A JPH025529A JP15717388A JP15717388A JPH025529A JP H025529 A JPH025529 A JP H025529A JP 15717388 A JP15717388 A JP 15717388A JP 15717388 A JP15717388 A JP 15717388A JP H025529 A JPH025529 A JP H025529A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- polycrystalline silicon
- silicon thin
- phosphorus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 45
- 239000010408 film Substances 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- 238000002844 melting Methods 0.000 claims abstract description 17
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 17
- 239000011574 phosphorus Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000011521 glass Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 3
- 239000011259 mixed solution Substances 0.000 claims abstract 3
- 230000008018 melting Effects 0.000 claims description 12
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000007789 gas Substances 0.000 abstract description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 238000000992 sputter etching Methods 0.000 abstract description 4
- 229910052786 argon Inorganic materials 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 238000010884 ion-beam technique Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 8
- 238000001035 drying Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 239000003870 refractory metal Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000005871 repellent Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 150000003017 phosphorus Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000002940 repellent Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 241000283690 Bos taurus Species 0.000 description 1
- -1 argon gas Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野 薄氷発明は多結
晶シリコン薄膜と高融点金イ膜との２層膜を有する半導
体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The invention relates to a method for manufacturing a semiconductor device having a two-layer film of a polycrystalline silicon thin film and a high melting point gold film.
従来の技術
半導体集積回路素子の微細化、高密度化に伴ない配線材
料として高融点金属が注目されている。2. Description of the Related Art As semiconductor integrated circuit devices become smaller and more densely packed, high-melting point metals are attracting attention as wiring materials.
高融点金属は従来のＡＩ配線と異なり９００１Ｅ程度で
の熱処理が可能な為、配線上の絶縁膜を熱処理ｊ７て平
坦化できる等の利点をもち、素子の微細化に有利である
。Unlike conventional AI wiring, high-melting point metals can be heat treated at a temperature of about 9001E, so they have the advantage that the insulating film on the wiring can be flattened by heat treatment, which is advantageous for miniaturization of elements.
第２図に従来の技術による高融点金属配線形成の工程順
断面図を示す。FIG. 2 shows a cross-sectional view of the process of forming high-melting point metal wiring according to a conventional technique.
第２図（、）に示す様にシリコン基板１上に層間絶縁膜
２を形成しコンタクトホール等を形成後、多結晶シリコ
ン薄膜３をＬＰＧＶＤ（減圧化学気相成長）法により形
成する。この多結晶シリコン薄膜３を低抵抗化する為、
気相拡散法によりＰＨ３ガスおよび０２ガス中で９００
℃稈度で熱処理し、リンを添加する。この際同図（１）
）に示す様に多結晶シリコン薄膜３上にはリンを含んだ
酸化膜であるリンガラス４が形成される。このリンガラ
ス４を希フッ酸によるウェットエツチングで除去し、水
洗後スピンドライにより乾燥する４、ここで多結晶シリ
コン薄膜３は撥水性である為リンガラス４除去後の表面
は撥水性表面となる。スピンドライによる乾燥の際に撥
水性表面では特定のパターン上にシミ状の異物８が形成
される。次に多結晶シリコン薄膜３上にスパッタ法ある
いはＣＶＤ法により高融点金属薄膜６を形成しく同図（
ｄ））、同図（ｅ）。As shown in FIG. 2(,), after forming an interlayer insulating film 2 on a silicon substrate 1 and forming contact holes, etc., a polycrystalline silicon thin film 3 is formed by LPGVD (low pressure chemical vapor deposition). In order to lower the resistance of this polycrystalline silicon thin film 3,
900 in PH3 gas and 02 gas by vapor phase diffusion method.
Heat treatment at ℃ culm and add phosphorus. At this time, the same figure (1)
), a phosphorus glass 4 which is an oxide film containing phosphorus is formed on the polycrystalline silicon thin film 3. This phosphorus glass 4 is removed by wet etching with dilute hydrofluoric acid, washed with water, and then dried by spin drying 4. Since the polycrystalline silicon thin film 3 is water repellent, the surface after the phosphorus glass 4 is removed becomes a water repellent surface. . During drying by spin drying, stain-like foreign matter 8 is formed on a specific pattern on the water-repellent surface. Next, a refractory metal thin film 6 is formed on the polycrystalline silicon thin film 3 by sputtering or CVD.
d)), same figure (e).
（ｆ）に示す様にホトリソグラフィー法およびドライエ
ツチング法により多結晶シリコン薄膜３と高融点金属薄
膜６の２層膜をパターニングし配線形成を行なう。As shown in (f), the two-layer film of polycrystalline silicon thin film 3 and refractory metal thin film 6 is patterned by photolithography and dry etching to form wiring.
発明が解決しようとする課題
この方法による２層配線膜の形成方法では前記の様に多
結晶シリコン薄膜３上にシミ状の異物８が形成され後工
程のパターニングの際、このシミ状異物８が対ドライエ
ツチングのマスクとなり高融点金属薄膜６がエツチング
されても異物下の多結晶シリコン薄膜３はエツチングさ
れず残存する。Problems to be Solved by the Invention In the method for forming a two-layer wiring film using this method, as described above, a stain-like foreign substance 8 is formed on the polycrystalline silicon thin film 3, and this stain-like foreign substance 8 is removed during patterning in a later process. Even if the high melting point metal thin film 6 is etched as a mask for dry etching, the polycrystalline silicon thin film 3 under the foreign matter is not etched and remains.
この為、配線間の短絡が生じ半導体装置の不良原因とな
る。For this reason, a short circuit occurs between the wiring lines, which causes a failure of the semiconductor device.
課題を解決するだめの手段
前記課題を解決する為に本発明による半導体装置の製造
方法は次のような手段をとる。Means for Solving the Problems In order to solve the above problems, the method for manufacturing a semiconductor device according to the present invention takes the following measures.
まず希フッ酸によシリンガラスを除去した後、スピン乾
燥前の最終洗浄で多結晶シリコン薄膜上に自然酸化膜を
形成し、表面親水性となる処理を行なう。First, after removing the syringe glass with dilute hydrofluoric acid, a natural oxide film is formed on the polycrystalline silicon thin film in the final cleaning before spin drying, and the surface is made hydrophilic.
次に高融点金属薄膜形成前にアルゴンガスなどの不活性
ガスイオンによるヌパッタエッチングにより前記多結晶
シリコン薄膜上の自然酸化膜を除去し、連続して同一試
料室内にて高融点金属薄膜を形成するものである。Next, before forming a high melting point metal thin film, the natural oxide film on the polycrystalline silicon thin film is removed by Nupatta etching using inert gas ions such as argon gas, and a high melting point metal thin film is continuously formed in the same sample chamber. It is something to do.
作 用
この方法による多結晶シリコン薄膜と高融点金属薄膜の
２層膜形成方法によれば次のような牛用がある。Function: According to this method of forming a two-layer film of a polycrystalline silicon thin film and a high melting point metal thin film, the following cattle products are available.
まず希フッ酸によるリンガラス除去後の最終洗浄で表面
親水性となっている為、スピン乾燥によるシミ状の異物
の発生が全く生じない。First, the surface is made hydrophilic by the final cleaning after removing phosphorus glass with dilute hydrofluoric acid, so no stain-like foreign matter occurs during spin drying.
また多結晶シリコン薄膜上の自然酸化膜を高融点金属薄
膜形成前のスパッタエッチによシ除去する事で多結晶シ
リコン薄膜と高融点金属薄膜との密着性も良く、膜はが
れ等の問題もない。In addition, by removing the natural oxide film on the polycrystalline silicon thin film by sputter etching before forming the high melting point metal thin film, the adhesion between the polycrystalline silicon thin film and the high melting point metal thin film is good, and there are no problems such as film peeling. .
すなわち良好な多結晶シリコン薄膜と高融点金属薄膜の
２層膜形成が可能で、高歩留りで信頼性の高い半導体装
置の製造が可能となる。That is, it is possible to form a two-layer film of a good polycrystalline silicon thin film and a refractory metal thin film, and it is possible to manufacture a semiconductor device with high yield and high reliability.
実施例
以下、本発明による半導体装置の製造方法を第１図に示
す工程順断面図により詳述する。EXAMPLES Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be explained in detail with reference to step-by-step sectional views shown in FIG.
まず第１図（ａ）に示す様にシリコン基板１上に層間絶
縁膜２を形成し、コンタクトホール等を形成した後、Ｌ
ＰＣＶＤ（減圧化学気相成長）法により多結晶シリコン
薄膜３を１５０ｎｍ形成する。First, as shown in FIG. 1(a), an interlayer insulating film 2 is formed on a silicon substrate 1, contact holes etc. are formed, and then L
A polycrystalline silicon thin film 3 with a thickness of 150 nm is formed by PCVD (low pressure chemical vapor deposition).
次に気相拡散法によりＰＨガスおよびｏ２ガス雰囲気で
９００ ℃、３０分の熱処理を行ない、多結晶シリコン
薄膜３にリンを添加し低抵抗化する。Next, a heat treatment is performed at 900° C. for 30 minutes in a PH gas and O2 gas atmosphere using a vapor phase diffusion method, and phosphorus is added to the polycrystalline silicon thin film 3 to lower its resistance.
この処理の後、同図（ｂ）に示す様に多結晶シリコン薄
膜３上には約２５ ｎｍのリンを含んだ酸化膜（リンガ
ラス）が形成されている。After this treatment, an oxide film containing phosphorus (phosphorus glass) of about 25 nm is formed on the polycrystalline silicon thin film 3, as shown in FIG. 3(b).
次にこのリンガラスをフッ酸と水の混合液によシ完全除
去し３０分の水洗後、連続して過酸化水素とアンモニア
と水の混合液で７ｏ℃、１ｓ分間の処理を行なう。この
処理で多結晶シリコン薄膜３上には同図（Ｃ）に示すよ
うに約２ｎｍの自然酸化膜６が形成される。Next, this phosphorus glass is completely removed with a mixture of hydrofluoric acid and water, and after washing with water for 30 minutes, a treatment is continuously performed for 1 second at 7° C. with a mixture of hydrogen peroxide, ammonia, and water. Through this process, a natural oxide film 6 of about 2 nm is formed on the polycrystalline silicon thin film 3, as shown in FIG.
次に高融点金属スパッタ蒸着装置において、まずアルゴ
ンガスによるイオンビームスパッタエツチング法により
多結晶シリコン薄膜３上の自然酸化膜５を除去する。連
続して同図（ｅ）に示す様にスパッタ蒸着法により高融
点金属薄膜６を形成し、２層膜を形成する。Next, in a high melting point metal sputter deposition apparatus, the natural oxide film 5 on the polycrystalline silicon thin film 3 is first removed by ion beam sputter etching using argon gas. Continuously, as shown in FIG. 6(e), a high melting point metal thin film 6 is formed by sputter deposition to form a two-layer film.
続いて同図（ｆ）、 （ｑ）に示す様にホトリソグラフ
ィー法およびドライエツチング法により多結晶シリコン
薄膜３と高融点金属薄膜６の２層膜をパターニングし、
配線形成を行なう。Subsequently, as shown in FIGS. 5(f) and (q), the two-layer film of the polycrystalline silicon thin film 3 and the high melting point metal thin film 6 is patterned by photolithography and dry etching.
Perform wiring formation.
発明の効果
以上の様に本発明による半導体装置の製造方法によれば
、シミ状の異物の発生がなく配線間の短絡が生じる心配
はない。Effects of the Invention As described above, according to the method of manufacturing a semiconductor device according to the present invention, there is no generation of foreign particles in the form of stains, and there is no fear of short circuits occurring between wiring lines.
すなわち良好な多結晶シリコン薄膜と高融点金属薄膜と
の２層膜形成が可能で、高歩留りで信頼性の高い半導体
装置の製造が可能である。That is, it is possible to form a two-layer film of a good polycrystalline silicon thin film and a refractory metal thin film, and it is possible to manufacture a highly reliable semiconductor device with high yield.
第１図は本発明による半導体装置の製造方法の工稈１噴
断面図、第２図は従来の技術による半導体装置の製造方
法の工程順断面図である。
１・・・・・・シリコン基板、２・・・・・・層間絶縁
膜、３・・・・・・多結晶シリコン、４・・・・・・リ
ンガラス、６・・・・・・自然酸化膜、６・・・・・・
高融点金属、Ｔ・・・・・・ホトレジスト、８・・・・
・・シミ伏冗物。
代１Ｊｌｊ人の氏ｒ ’ｆｉｌｌ’ｌ 中Ｉｔｓ
Ｆｆｆｌ、９３ １１カ１ ｎ／−、、ソコン基六FIG. 1 is a cross-sectional view of one culm of a semiconductor device manufacturing method according to the present invention, and FIG. 2 is a step-by-step cross-sectional view of a conventional semiconductor device manufacturing method. 1... Silicon substrate, 2... Interlayer insulating film, 3... Polycrystalline silicon, 4... Phosphorus glass, 6... Nature Oxide film, 6...
High melting point metal, T... Photoresist, 8...
...Stains are hidden. Mr. R 'fill'l Inside Its
Fffl, 93 11ka1 n/-,, socon group 6
Claims (1)
結晶シリコン薄膜上にリンガラスを形成した後、前記リ
ンガラスを希フッ酸により除去し、その後連続して過酸
化水素、アンモニア、水の混合液で洗浄処理する工程と
、不活性ガスイオンによるスパッタエッチング法を用い
て洗浄処理により前記多結晶シリコン薄膜上に形成され
た自然酸化膜を除去し、連続して同一試料室内にて前記
多結晶シリコン薄膜上に高融点金属薄膜を形成する工程
とを含むことを特徴とする半導体装置の製造方法。After adding phosphorus to a polycrystalline silicon thin film using a thermal diffusion method to form phosphorus glass on the polycrystalline silicon thin film, the phosphorus glass is removed with dilute hydrofluoric acid, and then hydrogen peroxide, ammonia, and water are successively added to the polycrystalline silicon thin film. The natural oxide film formed on the polycrystalline silicon thin film is removed by the cleaning process using a mixed solution of 1. A method of manufacturing a semiconductor device, comprising: forming a high melting point metal thin film on a polycrystalline silicon thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15717388A JPH025529A (en) | 1988-06-24 | 1988-06-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15717388A JPH025529A (en) | 1988-06-24 | 1988-06-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH025529A true JPH025529A (en) | 1990-01-10 |
Family
ID=15643786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15717388A Pending JPH025529A (en) | 1988-06-24 | 1988-06-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH025529A (en) |
-
1988
- 1988-06-24 JP JP15717388A patent/JPH025529A/en active Pending
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