JPH0255801B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a digital servo device, and particularly to a video tape recorder (hereinafter referred to as VTR).
The present invention is suitable for applications that require highly accurate rotational frequency and rotational phase, such as rotating head motors and capstan motors.

In general, VTRs use a helical scan method for recording and playback using a rotating video head. Tape transport is obtained by a capstan motor, and rotation of the rotating video head for obtaining recording and playback is obtained by a rotating head motor.
Here, a servo device is provided for each of the capstan motor and the rotary head motor.

When the capstan motor is in recording mode,
It is controlled to obtain a stable and constant rotational frequency and phase. In addition, in the playback mode, the rotation frequency is determined according to the specified double speed playback (usually, double speed, triple speed, etc.), and at this time, for example, phase control such as phase synchronization with the control pulse recorded on the tape is performed. It is done.

On the other hand, the rotating head motor is set to a stable and constant frame frequency when in recording mode.
At this time, it is controlled to be phase synchronized with the multi-modal synchronization signal. In playback mode, the rotation is set to a stable, constant frame frequency.

As mentioned above, for VTRs, the automatic frequency control (AFC) circuit and automatic phase control (APC) circuit for the capstan motor are used.
An AFC circuit and an APC circuit are also provided for the rotary head motor. In this way, a method for processing AFC circuits and APC circuits using digital signals has been realized. This is also described in detail in Japanese Patent Application No. 52-113864, which was previously filed by the applicant. This digital servo device basically consists of a counter, first and second latch circuits, a subtraction circuit, and the like. Now, we will explain the APC circuit of a rotating video head when it is in recording mode. The counter cycles and counts clock pulses. A rotation detection pulse obtained by detecting the rotation of the rotary head motor is applied as a latch pulse to the first latch circuit, and a 1/2 vertical synchronization signal is applied to the second latch circuit.
A signal whose frequency is divided into (in recording mode) is added as a latch pulse. The first and second latch circuits each latch the count value of the counter at that time when a latch pulse is input to each of them. Therefore, by calculating the difference between the latch contents of the first and second latch circuits, it is possible to obtain, for example, the phase difference between the rotation detection pulse and the vertical synchronization signal. The magnitude of this phase difference is expressed as a digital value (time can also be calculated from the clock cycle). If the digital value representing this phase difference is a preset value, the state at that time is stable; if the value changes, the changed amount is corrected and the state is brought into a stable state ( phase lock). Therefore, pulse width modulation is performed according to the digital value, and the pulse width modulation output is converted into direct current by a filter and supplied to the motor drive circuit. In this way, the APC circuit locks the rotational phase of the rotary head motor to the vertical synchronization signal, but an AFC circuit is also provided as a control system for this motor.

A servo device system having an APC circuit and an AFC circuit can be represented as shown in FIG. That is, the rotation detection pulse of the motor 11 is input to the AFC detection device 12 and a frequency error is detected. The frequency control voltage output from this AFC detection device 12 is applied to a control terminal of a motor drive circuit 14 via a synthesizer 13. On the other hand, the motor rotation detection pulse is converted by a frequency divider 15 to a frequency suitable for performing phase comparison, and the phase comparator 16 compares the phase with a reference signal (for example, a signal obtained by dividing the vertical synchronization signal by 1/2). be compared. The phase error voltage obtained from this phase comparator 16 is passed through a loop filter 17 to a synthesizer 1.
3, the signal is combined with the frequency control voltage and input to the motor drive circuit 14. The purpose of the loop filter 17 is to provide an integral characteristic here and to reduce the steady phase error.

For example, a processing circuit as shown in FIG. 2 has been considered as a digital processing circuit for obtaining the above-mentioned frequency error voltage or phase error voltage.

In FIG. 2, 21 is a binary synchronous counter to which a clock pulse _CK1 is input. This 2
The carrier of the synchronized counter 21 is a flip-flop circuit 2 that creates a pulse width modulation (PWM) output.
4 set input. The coincidence output of the comparator 22 is used as the reset input of the flip-flop circuit 24. This comparator 22
compares the count contents of the binary synchronous counter 21 and the latch contents of the register 23.

On the other hand, 25 is a sequence pulse generator, and data input terminals 28 and 29 of this sequence pulse generator 25 are inputted with a measurement pulse 28P and a reference pulse 29P. The sequence pulse generator 25 also includes a clock pulse _CK2 for data transfer.
can also be added. Now, when the reference pulse 29P is input, the sequence pulse generator 25 sets a constant constant to the presettable up counter 26 (flip-flop circuits Q0 to Q13) via the NAND circuit G23 and the inverter G24 according to the rising edge of the reference pulse. The bit counter Q14 for carry holding is also cleared. From this point on, the presettable up counter 26 will count the clock pulses _CK2 . Next, when the measurement pulse 28P is input, the input conditions of the NAND circuits G19 and G20 change at the rising edge of the measurement pulse 28P, and the clock pulse is sent to the presettable up counter 26.
CK ₂ is prohibited from entering. Then, at the timing of the latch pulse obtained from the NAND circuit G22 and the inverter G21, the count contents of the presettable up counter 26 are transferred to the register 23.
is memorized.

As a result, the flip-flop circuit 24 outputs a pulse width modulated PWM signal having a pulse width corresponding to the time difference between the reference signal 29P and the measurement pulse 28P.
You get waves.

In this case, the upper bits of the presettable up counter 26 (flip-flop circuit Q11
-Q13) are operated on by a NAND circuit G25, and the results are latched in a latch circuit Q26. Furthermore, the presence or absence of a carry in the presettable up counter 26 is latched in a latch circuit Q27 via a bit counter Q14. Therefore, now the latch circuit Q26,Q
If the output of 27 is , then the NAND circuit G
The calculation output of 15, G16, G17 is・
(PWM+). This is the reference signal 29P
If the time difference between and the measurement pulse 28P is large and an overflow state of the presettable up counter 26 occurs, or if the time difference between them is too small and is below a predetermined control range, the NAND circuit G17 is activated regardless of the pulse width of the PWM wave. This is to fix the output of

Using the above system, the AFC circuit,
When the APC circuit is formed, it will look like the one shown in Figure 3. In FIG. 3, the same parts as in FIG. 2 will be explained using the same symbols. That is, the carry of the binary synchronous counter 21 is the flip-flop circuit 3 on the AFC side.
This is used as the set input for 4. The coincidence output of the comparator 32 is used as the reset input of the flip-flop circuit 34. This comparator 32 compares the count contents of the binary synchronous counter 21 and the latch contents of the register 33.

Although not shown, the contents of a counter similar to the presettable up counter 26 described above are latched in the register 33. On the AFC circuit side, measure the interval between multiple pulses obtained per revolution of the motor. Therefore, instead of the reference pulse and measurement pulse shown in FIG. 2, a rotation detection pulse is added, and its period is measured by a presettable up counter. This AFC
Even on the circuit side, PWM
Wave calculations are performed by NAND circuits G32, G33, and G34. As a result, a PWM wave is obtained from the NAND circuit G34 when it is within the measurement range, and is fixed at a constant level when it is outside the measurement range.

Here, the final output of the PWM wave on the APC circuit side and the outputs of the latch circuits Q54 and Q55 on the AFC circuit side are related by NAND circuits G33, G35, and G36. This is because it is meaningless to obtain an output from the APC side when the AFC circuit side is not stable, and instead causes disturbance in the AFC operation. Therefore, if you start a motor equipped with this servo system from zero rotations, the motor will reach a certain rotation speed (AFC pull-in range).
Until this happens, the phase comparison output maintains zero (duty 0%) or "1" (duty 100%).

Considering the initial operation of the above system, the voltage output for driving the motor is as shown in FIG. In FIG. 4, a curve 40 shows the motor drive voltage, a curve 41 shows the change in the motor rotation speed, and the range indicated by (N1←→N2) is the range in which the AFC circuit pulls the motor into a predetermined rotation speed. Therefore, the PWM wave on the APC circuit side is fixed at a constant duty until the motor reaches a certain rotation speed. Fourth
The figure shows a case where the duty is zero.
Next, when the motor rotation speed reaches a certain value, a PWM wave on the APC circuit side is obtained.
The APC voltage (shown by curve 42) gradually rises;
The target voltage VP will be reached. This rising period 44 is mainly influenced by the loop filter 17 described in FIG. 1. This loop filter 17
As mentioned above, this is intended to provide an integral characteristic here and to reduce the phase error (fluctuation) during steady state.

As described above, in the digital processing system described above, there is a factor that delays the rise of the APC voltage at the time of starting the motor, and it takes time until the phase lock state is achieved.

This invention was made with attention to the above-mentioned points, and it is possible to reduce the start-up time of the motor (until phase lock is achieved), and also to reduce the initialization of the internal flip-flop circuit when the power is turned on, which is unique to digital circuits. Another object of the present invention is to provide a digital servo device that does not require initialization.

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 5, the same parts as in FIGS. 2 and 3 will be explained using the same reference numerals. In the case of this device,
The output of the latch circuit Q54 on the AFC circuit side is applied to the second input terminal of the NAND circuit G43, and further applied to the first input terminal of the NAND circuit G44 via the inverter G42. A binary synchronous counter 2 is connected to the first input terminal of the NAND circuit G43.
1, a pulse obtained in the middle of one cycle (carry output period) is added. Furthermore, the PWM wave on the APC circuit side obtained from the NAND circuit G17 is applied to the second input terminal of the NAND circuit G44. The outputs of the NAND circuits G43 and G44 are connected to the first input terminal and the second input terminal of the NAND circuit G45.
The output of this NAND circuit G45 is applied to the input terminal and is derived via an inverter G46.

On the other hand, on the AFC circuit side, NAND circuit G3
4 output is NAND circuit G56, inverter G57
In this case, conditions are set by a circuit constituted by flip-flop circuits Q61, Q62, AND circuit G51, and NAND circuits G52, G53, G54, and G55.

That is, the latch pulse (corresponding to the motor frequency rotation detection pulse) on the AFC circuit side is input to the clock input terminal of the flip-flop circuit Q61, and the presettable counter on the APC circuit side is input to the clock input terminal of the flip-flop circuit Q62. A load pulse (corresponding to a reference signal) is input. Flip-flop circuit Q61, Q62
"1" is given to the data input terminal of.
The outputs Q and Q of the flip-flop circuit Q61 are respectively applied to the first input terminals of the NAND circuits G52 and G53, and the outputs Q and Q of the flip-flop circuit Q62 are respectively applied to the second input terminals of the NAND circuits G53 and G52. The outputs Q of the flip-flop circuits Q61 and Q62 are respectively applied to the first and second input terminals of the AND circuit Q51,
The output of this AND circuit G51 is applied to the clear terminal of each flip-flop circuit Q61, Q62. Next, the outputs of the NAND circuits G52 and G53 are applied to the first and second input terminals of each of the NAND circuits G54 and G55. NAND circuit G54, G55
constitutes a flip-flop circuit, the output of which is applied to the first input terminal of a NAND circuit G56.

The above-mentioned flip-flop circuits Q61 and Q6
2. NAND circuit G52, G53, G54, G5
5. AND circuit G51 etc. is connected to the rotation frequency _FG (frequency of rotation detection pulse) on the AFC circuit side.
The frequency is compared with the reference signal frequency _Ref on the APC circuit side. Then, when _R ef > _FG , the NAND circuit G56 is made non-conductive, and the AFC output is made to have a duty of zero. In other words, at this time, the rotation frequency of the motor is determined by the reference signal (for example, the vertical synchronization signal)
This is because it is smaller than the frequency and means that it is not within the frequency pull-in range. Therefore, at this time, a voltage close to the maximum power supply voltage is applied as the motor drive voltage. This is the range of period 45 with reference to FIG.

On the other hand, in this case, the output of the latch circuit 33 is naturally "1". As a result, NAND circuit G43 becomes conductive, NAND circuit G44 becomes non-conductive, and APC
On the circuit side, a PWM wave with a constant duty of 50% is forcibly obtained from a binary synchronous counter. Note that this duty is a target value that has been set in advance for the APC output that will be obtained when the motor phase is locked, so it is not necessarily
It doesn't have to be 50%. In this way, by forcibly setting the PWM wave on the APC circuit side to the target value until the rotation speed reaches the AFC pull-in range, the time it takes for the motor to phase lock can be significantly shortened. Can be done. That is, in this case
This is because the APC output voltage becomes like the curve 46 shown in FIG. 4, and the rising period 44 can be eliminated. At this time, since it is within the AFC pull-in range, the output of the latch circuit Q54 is naturally "0", and the NAND circuit G44 is conductive.
NAND circuit G43 becomes non-conductive.

FIG. 6 shows a servo device equipped with a digital processing system as described above, in this case a digital servo system for a rotary head motor of a VTR. In FIG. 6, 51 is a rotary head motor, and this rotary head motor 5
The first rotation system is provided with rotation detection means. As the rotation detection means, for example, a frequency detection pulse generator 52 for detecting rotation frequency and a phase detection pulse generator 53 for phase detection are provided. These pulse generators have a structure in which, for example, a permanent magnet is attached to a rotating plate, a magnetic head is placed at a fixed position, and pulses are obtained from the magnetic head as the permanent magnet rotates. The frequency detection pulse FG and the phase detection pulse PG are input to the digital processing section 55 via the Schmitt amplifier 54. A reference signal Ref (for example, a signal obtained by dividing the vertical synchronization signal into 1/2, a control pulse) is also input to the digital processing section 55.
Furthermore, clock pulses CK ₁ and CK ₂ are also input.
This digital processing section 55 is as described above.
This is the part that derives the PWM wave, and is on the AFC circuit side.
The PWM wave is derived from the output terminal 55F, and the PWM wave on the APC circuit side is derived from the output terminal 55P. The PWM wave obtained at the output terminal 55F is passed through the filter 5
6 and then input to the motor drive circuit 58 via a resistor _R2 . Further, the PWM wave obtained at the output terminal 55P on the APC circuit side is input to the motor drive circuit 58 via a loop filter and a resistor _R7 . Resistors R ₈ and R ₉ are provided for loop gain adjustment. Now filter 56
consists of a resistor R ₁ and a capacitor C ₁ , and a filter 5
7 is composed of resistors R ₅ and R ₆ and capacitors C ₄ and C ₅ . Also, the motor drive circuit 58
is configured such that the output of the operational amplifier OPA is applied to the common base of the transistors Tr ₂ and Tr ₃ via a resistor R ₄ . And the transistor
The common emitters of Tr ₂ and Tr ₃ are connected to the motor 51 and to the inverting input terminal of the operational amplifier OPA via a series circuit of a capacitor C ₃ and a resistor R ₃ . Further, a capacitor C ₂ is connected in parallel to the series circuit of the capacitor C 3 and _the resistor R ₃ . The collector of transistor Tr ₂ is connected to power supply B1
connected to. Further, the collector of the transistor Tr ₁ is connected to the bases of the transistors Tr ₂ and Tr ₃ . This transistor _Tr1 is for starting and stopping the motor 51, and when it is off, the motor 51 rotates, and when it is on, the motor 51 is turned off.

For digital phase comparison and frequency discrimination output,
In other words, the values of the resistors R ₁ and R ₅ are set to be sufficiently large compared to the output impedance of the digital processing section 55.

Gain GA after digital processing section of AFC loop
GA=Z ₂ /Z ₁ , Z ₁ =R ₁ +R ₂ , Z ₂ =1/1/R ₃ +1/SC ₃ . Here, the gain G _AFc on the frequency discrimination (AFC circuit) side is set as follows.

E _B1 *R ₁ +R ₂ /R ₁ +R ₂ +R ₃ >E _B2 *1/2 ...(1) In this equation, the left side is the AFC detection output terminal voltage,
This is the negative terminal voltage of the operational amplifier OPA when the voltage across the capacitor _C3 is zero, and is the voltage when the transistor _Tr1 shifts from the on state to the off state (at the time of rotation start). Also, the right side is
This voltage is equal to the target voltage value on the APC detector side.

The gain of AFC detection is the rotation frequency detection pulse FG
If the frequency _FG is the linear range time (until the pull-in range is reached) is ΔT, then ΔT=1/ck ₁ ×2 ^b _FG =N×a. _FG is expressed as (motor rotation speed N)×(number of pulses/1 rotation). Further, number of pulses/one rotation=a, and cki is the frequency of the clock pulse. Here, by selecting a, b, and ck ₁ , settings can be made so that equation (1) is satisfied.

As described above, the present invention can provide a digital servo device that can reduce the startup time of the motor and quickly achieve a stable phase lock state.

[Brief explanation of drawings]

Figure 1 is a basic explanatory diagram of the servo device, Figure 2 is a circuit diagram showing a part of the digital processing section of the digital servo device, and Figure 3 is a part of the digital servo device with AFC and APC circuits. A circuit configuration diagram, FIG. 4 is an operation explanatory diagram shown to explain the operation of a motor operated by a digital servo device,
FIG. 5 is a circuit configuration diagram showing an embodiment of the present invention, and FIG. 6 is a configuration diagram showing a specific example of use of the device of the present invention. 21... Binary synchronous counter, 22, 32... Comparator, 23, 33... Register, 24, 34... Flip-flop circuit, 26... Presettable up counter, G15 to G17, G33 to G34...
NAND circuit, G43-G45, G52-G56...
NAND circuit, G51...AND circuit, Q61, Q6
2...Flip-flop circuit.

Claims (1)

[Claims] 1 Sample the interval between the rotational frequency detection pulses representing the rotational frequency of the motor as a digital value, use the digital value to obtain a pulse width modulated wave for frequency control with a pulse width corresponding to this value, and pass this through a filter to control the motor. Automatic frequency control means added to the drive circuit, samples a digital value between the rotational phase detection pulse representing the rotational phase of the motor and the reference signal, and uses the digital value to control the rotational phase with a pulse width corresponding to this value. In a digital servo device equipped with an automatic phase control means that obtains a pulse width modulated wave, passes it through a filter, and applies it to the motor drive circuit, the frequencies of the reference signal and the rotation frequency detection pulse are compared, and the frequency of the reference signal is determined. means for turning off the pulse width modulated wave for frequency control only when the frequency is high; and means for turning off the pulse width modulated wave for frequency control only when the frequency is high; and means for forcibly setting the pulse width of the pulse width modulated wave on the automatic phase control means side to a target when a digital value outside the frequency pull-in range is being sampled. Digital servo device.