JPH0258393A - Printed wiring board structure - Google Patents

Printed wiring board structure

Info

Publication number
JPH0258393A
JPH0258393A JP63209873A JP20987388A JPH0258393A JP H0258393 A JPH0258393 A JP H0258393A JP 63209873 A JP63209873 A JP 63209873A JP 20987388 A JP20987388 A JP 20987388A JP H0258393 A JPH0258393 A JP H0258393A
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
chip
chip component
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63209873A
Other languages
Japanese (ja)
Inventor
Hirobumi Fukuda
福田　博文
Yoshihira Fukue
福江　賀平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63209873A priority Critical patent/JPH0258393A/en
Publication of JPH0258393A publication Critical patent/JPH0258393A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/26—Cleaning or polishing of the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To remove the fear of migration occurring and to mount chip parts in high density on the surface by providing taper holes at the parts of a printed wiring board that the bottoms of the chip parts are opposed. CONSTITUTION:Pads 5 are arranged corresponding to the electrodes 3 of chip parts 2 on the surface of a printed wiring board 1, and a taper hole 20 which is more largely opened on the nonmounting side is provided in each center of these arranged pads 5. And the electrode 3 of this chip part 2 is aligned with the pad 5, and then the pad 5 and the electrode 3 are bonded and connected through solder 6 by a solder reflow means, etc., so as to mount the chip part 2 on the surface of the printed wiring board 1. Accordingly, when the printed wiring board 1 is soaked and cleaned in the bath of organic solvent such as, e.g., trichloroethylene, etc., cleaning liquid flows in the bottom 2a part of the chip part 2 through the taper hole 20 from the nonmounting side of the printed wiring board, and cleaning is sufficiently done.

Description

【発明の詳細な説明】 〔概要〕 チップ部品を表面実装したプリント配線板構造に関し、 高密度実装してマイグレーションを発生する恐れがない
、プリント配線板構造を提供することを目的とし、 チップ部品を表面実装したプリント配ｗＡＦｉにおいて
、該チップ部品の底面に対応する該プリント配線板部分
に、非実装面側が拡開したテーパー孔を設けた構成とす
る。或いは、多層プリント配線板において、該チップ部
品の底面に対応する該多層プリント配線板（１０）部分
に、非実装面側が拡開したテーパー孔を設け、該テーパ
ー孔の内壁面に、導体層間を接続するスルーホール導体
層を設けた構成とする。[Detailed Description of the Invention] [Summary] The purpose of the present invention is to provide a printed wiring board structure in which chip components are surface-mounted, and which can be mounted at high density without causing migration. In the surface-mounted printed wiring AFi, a taper hole is provided in the printed wiring board portion corresponding to the bottom surface of the chip component, with the non-mounting surface side widened. Alternatively, in a multilayer printed wiring board, a tapered hole whose non-mounting side is widened is provided in a portion of the multilayer printed wiring board (10) corresponding to the bottom surface of the chip component, and an inner wall of the tapered hole is provided with a hole between the conductor layers. The configuration includes a through-hole conductor layer for connection.

〔産業上の利用分野〕[Industrial application field]

本発明は、チップ部品を表面実装したプリント配線板構
造に関する。The present invention relates to a printed wiring board structure in which chip components are surface mounted.

近年の電子部品及び電子機器は、軽薄短小傾向にあり、
同時に高密度化が一段と要求されている。In recent years, electronic parts and devices have become lighter, thinner, and smaller.
At the same time, higher density is required.

このような背景から、プリント配線板に実装する半導体
部品、コンデンサ、抵抗体等の搭載部品は、チップ型に
して小形化し、さらにこれらのチップ部品を、高密度に
プリント配線板に実装している。Against this background, components mounted on printed wiring boards, such as semiconductor components, capacitors, and resistors, are being miniaturized in the form of chips, and these chip components are being mounted on printed wiring boards with high density. .

一方、半田付は時のフラックスがプリント配線板の表面
に残留していると、フラックスに含有された塩素骨に起
因してチップ部品の電極間、或いはフラットリード間等
が導通状態となる。即ち、フラックスが残留していると
、所謂マイグレーションが発生する。マイグレーション
は、特に表面実装プリント板に発生し易い。On the other hand, during soldering, if the flux remains on the surface of the printed wiring board, conduction will occur between the electrodes of the chip component or between the flat leads due to the chlorine bones contained in the flux. That is, if flux remains, so-called migration occurs. Migration is particularly likely to occur on surface-mounted printed circuit boards.

このような理由からして、マイグレーションが発生し難
い表面実装のプリント配線板構造が強く要望されている
。For these reasons, there is a strong demand for a surface-mounted printed wiring board structure in which migration is less likely to occur.

〔従来の技術〕[Conventional technology]

第３図は、従来のプリント配線板構造を示す断面図であ
る。FIG. 3 is a sectional view showing a conventional printed wiring board structure.

第３図において、チップ部品２をプリント配線板１に表
面実装出来るように、チップ部品２の対向する一対の側
面、及び側面に繋がる底面の一部に、電極３を設け、一
方、プリント配線板１の表面に、チップ部品２の電極３
に対応して、バッド５を配列形成しである。In FIG. 3, electrodes 3 are provided on a pair of opposing side surfaces of the chip component 2 and a part of the bottom surface connected to the side surfaces so that the chip component 2 can be surface mounted on the printed wiring board 1. The electrode 3 of the chip component 2 is placed on the surface of the chip 1.
The pads 5 are arranged in a corresponding manner.

このような構成にして、パブド５上にスクリーン印刷等
してクリーム半田を塗布し、電極３をクリーム半田上に
合わせてチップ部品２を載せ、所謂半田リフロー法によ
り、バッド５と電極３とを半田６で接続固着して、チッ
プ部品２をプリント配線板１に表面実装している。With this configuration, cream solder is applied to pad 5 by screen printing, etc., chip component 2 is placed with electrode 3 on top of the cream solder, and pad 5 and electrode 3 are bonded together by a so-called solder reflow method. The chip component 2 is surface mounted on the printed wiring board 1 by connecting and fixing it with solder 6.

また、チップ部品によっては、電極を設けず、フラット
リードをチップ部品より導出して、このフラットリード
とバッドとを半田付は接着して、表面実装している。Further, depending on the chip component, electrodes are not provided, flat leads are led out from the chip component, and the flat leads and pads are soldered or bonded for surface mounting.

上述のように、チップ部品２を表面実装した後に、例え
ばトリクロロエチレン等の有機溶剤槽に浸漬してプリン
ト配線板１を洗浄し、フラックスを除去して、マイグレ
ーションが発生しないようにしている。As described above, after the chip components 2 are surface-mounted, the printed wiring board 1 is cleaned by immersing it in an organic solvent bath such as trichlorethylene to remove flux and prevent migration from occurring.

一方、チップ部品をより高密度に実装するために、導体
層を複数とし、導体層間をスルーホールで所望に接続し
た所謂多層プリント配線板が、近年広く用いられている
。On the other hand, in order to mount chip components at a higher density, so-called multilayer printed wiring boards, which have a plurality of conductor layers and connect the conductor layers as desired through through holes, have been widely used in recent years.

なお、スルーホールは一般に、チップ部品の底面を避け
た、他の実装領域に設けている。Note that the through holes are generally provided in other mounting areas, avoiding the bottom surface of the chip component.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら表面実装したチップ部品の底面とプリント
配線板の表面間の間隙は、０．１ｎ〜０．２龍と小さい
。したがって、チップ部品を近接して配設した場合には
、特に洗浄液がプリント配線板の全表面に十分にゆきわ
たらず、チップ部品に対向するプリント配線板の表面部
分、又はチップ部品の表面部分にフラックスが残留して
、マイグレーションが発生するという問題点があった。However, the gap between the bottom surface of the surface-mounted chip component and the surface of the printed wiring board is as small as 0.1 to 0.2 mm. Therefore, when chip components are placed close to each other, the cleaning liquid may not be sufficiently spread over the entire surface of the printed wiring board, and may not be applied to the surface area of the printed wiring board facing the chip components or the surface area of the chip components. There was a problem that flux remained and migration occurred.

本発明はこのような点に鑑みて創作されたもので、高密
度実装してマイグレーションを発生する恐れがない、プ
リント配線板構造を提供することを目的としている。The present invention was created in view of these points, and an object of the present invention is to provide a printed wiring board structure that can be mounted at high density without causing migration.

〔課題を解決するための手段〕[Means to solve the problem]

上記の目的を達成するために本発明は、第１図に例示し
たように、チップ部品２を表面実装したプリント配線板
ｌにおいて、チップ部品２の底面２ａに対応するプリン
ト配線板１部分に、非実装面側が拡開したテーパー孔２
０を設ける。In order to achieve the above object, the present invention, as illustrated in FIG. Tapered hole 2 with expanded non-mounting surface side
Set 0.

また、第２図に例示したように、多層プリント配線板１
０において、チップ部品２の底面２ａに対応する多層プ
リント配線板１０部分に、非実装面側が拡開したテーパ
ー孔２０を設け、テーパー孔２０の内壁面に、導体層間
を接続するスルーホール導体層２１を設ける。Further, as illustrated in FIG. 2, a multilayer printed wiring board 1
0, a tapered hole 20 whose non-mounting surface side is expanded is provided in a portion of the multilayer printed wiring board 10 corresponding to the bottom surface 2a of the chip component 2, and a through-hole conductor layer is provided on the inner wall surface of the tapered hole 20 to connect the conductor layers. 21 will be provided.

〔作用〕[Effect]

上述のように、プリント配線板にテーパー孔２０を設け
であるので、洗浄液がプリント配線板の非実装面側から
、チップ部品の底面間に、極めて容易に流れ込み、また
流出する。As described above, since the tapered hole 20 is provided in the printed wiring board, the cleaning liquid very easily flows from the non-mounted side of the printed wiring board to between the bottom surfaces of the chip components, and also flows out.

したがって、チップ部品が近接して配列した場合におい
ても、洗浄が十分に行われて、フラックスを完全に除去
することができる。即ち、マイグレーションが発生する
恐れがない。Therefore, even when chip components are arranged closely, cleaning can be performed sufficiently and flux can be completely removed. That is, there is no risk of migration occurring.

また、洗浄効果を向上させるテーパー孔２０の内壁面に
、スルーホール導体層２工を設けて、テーパー孔に、導
体層間を接続するスルーホールの機能を持たせている。Further, two through-hole conductor layers are provided on the inner wall surface of the tapered hole 20 to improve the cleaning effect, so that the tapered hole has the function of a through-hole that connects the conductor layers.

したがって、このスルーホールの占有面積だけチップ部
品の実質の実装領域が拡大され、高密度実装化が推進さ
れる。Therefore, the actual mounting area of the chip components is expanded by the area occupied by the through holes, promoting high-density packaging.

〔実施例〕〔Example〕

以下図を参照しながら、本発明を具体的に説明する。な
お、全図を通じて同一符号は同一対象物を示す。The present invention will be specifically described below with reference to the drawings. Note that the same reference numerals indicate the same objects throughout the figures.

第１図は、請求項１の発明の実施例の断面図、第２図は
、請求項２の発明の実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the invention according to claim 1, and FIG. 2 is a sectional view of an embodiment of the invention according to claim 2.

第１図において、プリント配線板１の表面にチップ部品
２の電極３に対応して、バッド５を配列形成し、この配
列したバッド５の中心部に、非実装面側が拡開したテー
パー孔２０を設けである。In FIG. 1, pads 5 are arranged and formed on the surface of a printed wiring board 1 in correspondence with the electrodes 3 of the chip component 2, and in the center of the arranged pads 5 is a tapered hole 20 that is widened on the non-mounting surface side. This is provided.

そして、チップ部品２のｔ極３をバッド５に位置合わせ
させ、半田リフロー手段等により半田６を介して、バッ
ド５と電極３とを接続固着して、チップ部品２をプリン
ト配線板１に表面実装しである。Then, the t-pole 3 of the chip component 2 is aligned with the pad 5, and the pad 5 and the electrode 3 are connected and fixed through the solder 6 using a solder reflow method or the like, and the chip component 2 is attached to the surface of the printed wiring board 1. It has already been implemented.

したがって、プリント配線板１を、例えばトリクロロエ
チレン等の有機溶剤槽に浸漬し洗浄すると、洗浄液がプ
リント配線板の非実装面側からテーパー孔２０を通って
、チップ部品２の底面２８部分に流れこみ、洗浄が十分
に行われる。即ち、チップ部品の底面とプリント配線板
間のフラックスが除去される。Therefore, when the printed wiring board 1 is washed by immersing it in an organic solvent bath such as trichlorethylene, the cleaning liquid flows from the non-mounting side of the printed wiring board through the tapered hole 20 and into the bottom surface 28 of the chip component 2. Cleaning is done thoroughly. That is, the flux between the bottom surface of the chip component and the printed wiring board is removed.

第２図において、１０は、表面導体層の他に、内導体層
１ｌ−Ｌｌｌ−２，ＩＬ３を備えた多層プリント配線板
である。In FIG. 2, 10 is a multilayer printed wiring board that includes inner conductor layers 1l-Lll-2 and IL3 in addition to the surface conductor layer.

多層プリント配線板１０の表面にチップ部品２の電極３
に対応して、バッド５を配列形成し、この配列したバッ
ド５の中心部に、非実装面側が拡開したテーパー孔２０
を設け、チルパー孔２ｏの内壁面にスルーホール導体層
２１を設けである。Electrodes 3 of chip components 2 are placed on the surface of multilayer printed wiring board 10.
A tapered hole 20 is formed in the center of the arranged pads 5, and the non-mounting surface side is widened.
A through-hole conductor layer 21 is provided on the inner wall surface of the chiller hole 2o.

そして、図示右側のテーパー孔２０のスルーホール導体
ｒ１ｉ２１に、内導体層１１−１と内導体層１１−２と
を接続している。また、図示左側のテーパー孔２０のス
ルーホール導体１！２１に、内導体層１１−１と内導体
層１ｆ−３とを接続している。The inner conductor layer 11-1 and the inner conductor layer 11-2 are connected to the through-hole conductor r1i21 of the tapered hole 20 on the right side of the figure. Further, the inner conductor layer 11-1 and the inner conductor layer 1f-3 are connected to the through-hole conductor 1!21 of the tapered hole 20 on the left side of the figure.

したがって第２図に示す上記テーパー孔２０は、洗浄効
果を向上させてマイグレーションの発生防止機能の他に
、スルーホールとしての機能を備えている。Therefore, the tapered hole 20 shown in FIG. 2 not only has the function of improving the cleaning effect and preventing the occurrence of migration, but also has the function of a through hole.

即ち、プリント配線板の表面において、このスルーホー
ルの占有面積だけ、チップ部品２の実質の実装領域が拡
大される。よって、高密度実装化が推進される。That is, on the surface of the printed wiring board, the actual mounting area of the chip component 2 is expanded by the area occupied by the through hole. Therefore, high-density packaging is promoted.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、チップ部品の底面に対向
するプリント配線板部分に、テーパー孔を設け、或いは
テーパー孔の内壁面にスルーホール導体層を形成したプ
リント配線板構造であって、マイグレーションが発生す
る恐れがなく、且つチップ部品を高密度に表面実装する
ことができる等、実用上で優れた効果がある。As explained above, the present invention provides a printed wiring board structure in which a tapered hole is provided in the printed wiring board portion facing the bottom surface of a chip component, or a through-hole conductor layer is formed on the inner wall surface of the tapered hole. This method has excellent practical effects, such as eliminating the possibility of occurrence of the problem and allowing chip components to be surface-mounted with high density.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は請求項Ｉの発明の実施例の断面図、第２図は請
求項２の発明の実施例の断面図、第３図は従来のプリン
ト配線板構造を示す断面図である。 図において、 ■はプリント配線板、 １０は多層プリント配線板、 ２はチップ部品、 ３は電極、 ５はバッド、 ６は半田、 １１−１．１１−２．　ＩＬ３は内導体層、２０はテー
パー孔、 ２１はスルーホール導体層をそれぞれ示す。 テーパー貴− ／グツノン′Ｌ乙Ｅ４げ１°オ反− 従来例の前面図 第　３　ロFIG. 1 is a sectional view of an embodiment of the invention according to claim I, FIG. 2 is a sectional view of an embodiment of the invention according to claim 2, and FIG. 3 is a sectional view showing a conventional printed wiring board structure. In the figure, ■ is a printed wiring board, 10 is a multilayer printed wiring board, 2 is a chip component, 3 is an electrode, 5 is a pad, 6 is solder, 11-1.11-2. IL3 indicates an inner conductor layer, 20 indicates a tapered hole, and 21 indicates a through-hole conductor layer. Taper Takashi/Gutunon'L Otsu E4 ge 1° Otaru - Front view of conventional example No. 3 B

Claims (1)

【特許請求の範囲】[Claims] （１）　チップ部品（２）を表面実装したプリント配線
板（１）において、 該チップ部品（２）の底面（２ａ）に対応する該プリン
ト配線板（１）部分に、非実装面側が拡開したテーパー
孔（２０）を設けたことを特徴とするプリント配線板構
造。 ２　チップ部品（２）を表面実装した多層プリント配線
板（１０）において、 該チップ部品（２）の底面（２ａ）に対応する該多層プ
リント配線板（１０）部分に、非実装面側が拡開したテ
ーパー孔（２０）を設け、 該テーパー孔（２０）の内壁面に、導体層間を接続する
スルーホール導体層（２１）を設けたことを特徴とする
プリント配線板構造。(1) In a printed wiring board (1) on which a chip component (2) is surface-mounted, the non-mounting surface side is expanded in the portion of the printed wiring board (1) corresponding to the bottom surface (2a) of the chip component (2). A printed wiring board structure characterized by having a tapered hole (20). 2. In a multilayer printed wiring board (10) on which a chip component (2) is surface-mounted, the non-mounting surface side is expanded in a portion of the multilayer printed wiring board (10) corresponding to the bottom surface (2a) of the chip component (2). A printed wiring board structure characterized in that a tapered hole (20) is provided, and a through-hole conductor layer (21) for connecting conductor layers is provided on an inner wall surface of the tapered hole (20).
JP63209873A 1988-08-24 1988-08-24 Printed wiring board structure Pending JPH0258393A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63209873A JPH0258393A (en) 1988-08-24 1988-08-24 Printed wiring board structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63209873A JPH0258393A (en) 1988-08-24 1988-08-24 Printed wiring board structure

Publications (1)

Publication Number Publication Date
JPH0258393A true JPH0258393A (en) 1990-02-27

Family

ID=16580054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63209873A Pending JPH0258393A (en) 1988-08-24 1988-08-24 Printed wiring board structure

Country Status (1)

Country Link
JP (1) JPH0258393A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08311772A (en) * 1995-05-15 1996-11-26 Ikeda Bussan Co Ltd Composition for backing carpet and production of carpet
WO2009096003A1 (en) * 2008-01-29 2009-08-06 Fujitsu Limited Mounting structure for chip capacitor, electronic device and mounting method
CN102915833A (en) * 2011-08-05 2013-02-06 株式会社村田制作所 Chip-component structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08311772A (en) * 1995-05-15 1996-11-26 Ikeda Bussan Co Ltd Composition for backing carpet and production of carpet
WO2009096003A1 (en) * 2008-01-29 2009-08-06 Fujitsu Limited Mounting structure for chip capacitor, electronic device and mounting method
JPWO2009096003A1 (en) * 2008-01-29 2011-05-26 富士通株式会社 Chip capacitor mounting structure, electronic device and mounting method
CN102915833A (en) * 2011-08-05 2013-02-06 株式会社村田制作所 Chip-component structure

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