JPH0258646B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a microprogram control device that loads a microprogram stored in a large capacity memory onto a buffer memory and executes it in the buffer memory.

BACKGROUND ART In information processing devices controlled by microprograms, the microprogram capacity is increasing in order to diversify functions and improve performance. On the other hand, in order to improve performance, it is necessary to shorten the machine cycle and reduce the cost of the equipment, so it is difficult to increase the capacity of the control memory unnecessarily.

As a solution to this kind of problem, JP-A-58-119052
A system having a buffer memory is proposed in Japanese Patent Application No. Conventionally, in this type of device that loads microprograms from large-capacity memory to high-speed buffer memory and executes them, the size of the block when loading to buffer memory is fixed, so there are very few microprograms that originally need to be loaded. However, one block of microprogram must be loaded,
On the other hand, if there are an extremely large number of microprograms to be loaded, there is a disadvantage that the block loading operation is started many times, resulting in loss, which reduces the overall processing performance.

Purpose of the Invention The purpose of the present invention is to provide a block number table that gives the number of blocks to be loaded from a large capacity memory to a high-speed buffer memory, to make the number of blocks to be loaded in one block loading operation variable, and to achieve lean optimization. An object of the present invention is to provide a microprogram control device that realizes a block loading operation.

Structure of the Invention The microprogram control device according to the present invention includes:
It consists of a large capacity memory, an address register, a buffer memory, an address array, a comparator, a block number table, and a load control circuit.

Mass memory stores a series of microprograms. The address register holds microinstruction addresses. The buffer memory holds part of the microprogram stored in the large capacity memory and is composed of a plurality of blocks. The address array has entries corresponding to a plurality of blocks in the buffer memory. The comparator is a circuit that compares the output of the address array with part of the contents of the register to confirm whether or not a microinstruction to be executed is held in the buffer memory. The block number table gives the number of blocks to be loaded in one load operation from the large capacity memory to the buffer memory. The load control circuit is a circuit for controlling loading operations for the number of blocks specified by the block number table.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

The microprogram control system according to the present invention includes an address register 1, a buffer memory 2,
It is composed of an address array 3, a comparator 4, a block number table 5, a large capacity memory 6, and a load control circuit 7.

The microprogram in this example is 65536
It has a word capacity and its microinstruction address consists of 16 bits.

Referring to FIG. 1, register 1 is a register for holding a 16-bit microinstruction address, buffer memory 2 is a memory having a capacity of 4096 words, and address array 3 is an element having 256 entries. Buffer memory 2 is divided into 256 blocks of 16 words each, each block corresponding to each entry in address array 3. Buffer memory 2 is given bits 4-15 of register 1 as address information, and address array 3 is given bits 4-11 as address information. Each entry in address array 3 stores bits 0 to 3 of the microinstruction address of the microinstruction held in the corresponding block of buffer memory 2. Comparator 4
is bits 0-3 of register 1 and address array 3
It is detected whether the microinstruction corresponding to the microinstruction address held in the register 1 is held in the buffer memory 2 or not. Block number table 5 is a block number table consisting of 256 items using bits 0 to 7 of register 1 as index information. The large capacity memory 6 consists of an area for storing 65536 words of microprograms. The microprograms compared on this large capacity memory are divided into groups of 256 words each, and each group is further divided into 16 blocks of 16 words. Each group corresponds to each item in the block number table 5, and the number of blocks to be loaded when loading the microinstructions in the group from the large capacity memory 6 to the buffer memory 2 is given from the block number table 5. The load control circuit 7 transfers data from the large capacity memory 6 to the buffer memory 2.
This circuit controls the loading operation of microinstructions to the block in block units, and controls the block loading to be performed by the number of blocks given from the block number table 5.

Next, the operation of the embodiment shown in FIG. 1 will be described in detail. First, when a microinstruction address is set in the address register 1, one word of the buffer memory 2 corresponding to the contents of the register 1 is read out to the output signal line 11. At the same time, one entry of address array 3 corresponding to the contents of register 1 is read out to output signal line 12 and compared with bits 0 to 3 of register 1 in comparator 4. If the microinstruction corresponding to the contents of register 1 is held in buffer memory 2, then
The output signal line 11 is enabled and the load control circuit 7
is not started. However, if the corresponding microinstruction is not held in the buffer memory 2, the output signal line 11 is disabled and the load control circuit 7 is activated to start a block load operation via the signal line 13. It will be done. At this time, from block number table 5 to signal line 1
The number of blocks "N" (N is an integer greater than or equal to 1) to be loaded into register 1 is read out, and the output bit 0 of register 1 is read out.
.about.11 are supplied to the load control circuit 7. The load control circuit 7 receives these information, sequentially reads "16×N" words from the large capacity memory 6 starting from the first word of the block containing the microinstruction corresponding to the contents of the register 1, and writes them to the corresponding address in the buffer memory. At the same time, the contents held in bits 0 to 3 of register 1 are sequentially written to the corresponding N entries of address array 3. When the above process is completed, the microinstruction corresponding to the microinstruction address held in the register 1 is read out to the output signal line 11 of the control memory 2, and the bit 0 of the register 1 is read out to the output signal line 12 of the address array 3. Since the same contents as .about.3 are read out, comparator 4 indicates that the corresponding microinstruction is held in buffer memory 2, and output signal line 11 is enabled.

Effects of the Invention The present invention has the advantage of making it possible to vary the number of microinstruction words when loading from a large capacity memory to a high-speed buffer memory, and by realizing an optimized block loading operation with no waste. It has the effect of improving performance.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, 1...Register, 2...Buffer memory, 3...Address array, 4...Comparator, 5...Block number table, 6...Large capacity memory, 7...Load control circuit, 11- 14...Signal line.

Claims (1)

[Scope of Claims] 1. A large-capacity memory for storing a microprogram, an address register for holding a microinstruction address, and a buffer memory consisting of a plurality of blocks for holding a part of the microprogram in block units. an address array having entries corresponding to each of the plurality of blocks of the buffer memory; and a microinstruction to be executed on the buffer memory by comparing a portion of the contents held in the address register with the output of the address array. The microprogram stored in the large-capacity memory is divided into a plurality of microinstruction groups each consisting of one or more blocks. a block number table having an entry corresponding to a microinstruction group and giving the number of blocks to be loaded when the microinstruction is loaded from the large capacity memory to the buffer memory; and a block number table that indexes the block number table. A microprogram control device comprising: a load control circuit for controlling the load operation for the number of blocks obtained in units of one or more blocks.