JPH0115090B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Description of the technical field to which the invention pertains) The present invention relates to a microprogram control method for executing a part of a microprogram loaded into a buffer memory from a large capacity memory on the buffer memory.

(Description of Prior Art) Information contained in one word of a microinstruction includes a lot of information that is originally used only in some microinstructions. For example, when specifying the operation of an arithmetic processing unit (ALU: Arithmetic and Logic Unit), binary arithmetic operation functions, decimal arithmetic operation functions, logical operation functions, etc. can be defined, but each function must be usable by all microprograms. There isn't. In other words, when the entire microprogram is divided into multiple blocks with a certain number of words as units, each block must be configured so that it can realize at least one of the three functions of the arithmetic processing unit. Good. Focusing on this point, a patent application filed in 1974 shortened the bit length of microinstructions by providing one decode mode for each block of control memory and placing a decode mode memory to hold these modes.
This is proposed in a microprogram control device described in No. 152664 (Japanese Patent Application Laid-open No. 74749/1983).

Over time, the capacity of microprograms is increasing day by day with the diversification of functions and demands for improved performance of information processing devices. However, increasing the size of the control memory to meet these demands increases machine cycles and equipment costs, resulting in a substantial performance drop.
As one solution to this problem, a method using a low-cost large-capacity memory and a high-speed buffer memory equipped with an address array is proposed in Japanese Patent Application No. 57-1596 (Japanese Unexamined Patent Publication No.
58-119052) is proposed in the microprogram control method described in JP-A No. 58-119052).

However, these microprogram control devices and microprogram control methods still have the disadvantage of requiring a large amount of hardware because the address array does not contain information corresponding to the contents of the decode mode memory.

(Description of Object of the Invention) The object of the present invention is to provide a microprogram control device described in Japanese Patent Application No. 54-152664, and
The above drawbacks of the microprogram control method described in No. 1596 are solved, and management information for the block to be processed and control information commonly used in the process of executing microinstructions within the block are stored in the address array. It is an object of the present invention to provide a microprogram control method which is realized by holding the bit length of the microinstruction and reducing the size of the control memory.

(Description of structure and operation of the invention) The microprogram control system according to the present invention includes first to third registers, a buffer memory, an address array, an address comparator, a flip-flop, a decoder, and a large capacity memory. This was realized by doing so.

The first register is for holding the address of a microinstruction and operates as an address register. The buffer memory temporarily stores part of the microprogram in blocks. The second register is for holding microinstructions read from the buffer memory and operates as a microinstruction register. The address array holds block management information for the microprograms stored in the buffer memory and control information commonly used for decoding microinstructions in the process of executing microinstructions in blocks. It has entries corresponding to blocks. The third register is for holding control information read from the address array and operates as a control register. The address comparator compares the contents of the first register with block management information to detect whether or not the expected microinstruction exists inside the buffer memory. In the flip-flop, the address comparator indicates a match, and if there is a corresponding microinstruction in the buffer memory, state 1 is set; otherwise, state 0 is set. The decoder operates only when the state of the flip-flop is 1, decodes the contents of the second and third registers, and sends necessary control signals to each control section inside the system. A large capacity memory is made up of a plurality of blocks and is a memory for holding microprograms, and includes control information corresponding to each block.

(Description of Examples) Next, the present invention will be described in further detail with reference to the drawings.

One embodiment of the microprogram control system according to the present invention includes first to third registers 1, 3, 5, buffer memory 2, address array 4, address comparator 6, flip-flop 7, decoder 8, This is realized by a device equipped with a capacity memory 9.

In FIG. 1 showing one embodiment of the present invention, a first
The register 1 is an address register for holding the address of a microinstruction, the buffer memory 2 is a memory for holding a part of the microprogram read from the large capacity memory 9 in block units, and the second register 3 is a buffer memory 2. This is a microinstruction register for holding microinstructions read from the microinstruction register. The address array 4 holds block management information for the microprograms stored in the buffer memory 2 and control information commonly used in the process of executing microinstructions within the block. It has a corresponding entry. Third
The register 5 is a control information register for holding the control information read out from the address array 4. The address comparator 6 uses the block management information read from the address array 4 and a part of the microinstruction address held in the first register 1 to determine whether the expected microinstruction exists inside the buffer memory 2. This is a comparator for detecting whether or not the flip-flop exists, and sets the state of the flip-flop 7 to a logic value 0 if it does not exist, and sets the state of the flip-flop 7 to a logic value 1 if it exists. The decoder 8 has the second register 3 and the third
This is a decoder for inputting the contents held in the register 5 of the flip-flop 7 and for sending a control signal to each control section in the system when the state of the flip-flop 7 is 1. The large capacity memory 9 is made up of a plurality of blocks and is a memory for holding microprograms, and includes control information corresponding to each block.

Hereinafter, the operation of this embodiment will be explained step by step with reference to FIG. First, the address of the microinstruction to be executed is set in the first register 1. Next, the microinstruction inside the buffer memory 2 is read out to the second register 3 in accordance with the address set in the first register 1. At the same time, the corresponding entry is read from the address array 4 and control information commonly used within the block containing the microinstruction is set in the third register 5. At the same time, the address comparator 6 determines whether the microinstruction read from the buffer memory 2 is to be executed. If this microinstruction is to be executed, the state of the flip-flop 7 is set to logic 1 and the data held in the first register 3 and the second register 5 are sent to the decoder 8. is valid. Upon receiving this, the decoder 8 sends a control signal to each control unit in the system, calculates this microinstruction, and executes processing. If the above read microinstruction is not to be executed, the state of the flip-flop is set to logic 0.
, and instructs the decoder 8 that the data in the second register 3 and third register 5 are invalid. At the same time, the large-capacity memory 9 is accessed by accessing the microinstruction address held in the first register 1, and storing the block containing the corresponding microinstruction and the microinstruction when executing the internal microinstruction. Gives an instruction to load control information commonly used for instruction decoding. The large-capacity memory 9 sequentially stores all the microinstructions in the above block and transfers them to the buffer memory 2.
At the same time, control information and block management information commonly used by the microinstructions inside the block are written into the corresponding entry of the address array 4. When the above process is completed, the address held in the first register 1 is accessed again, the corresponding contents of the buffer memory 2 are read out, and the contents are set in the second register 3. At the same time, the corresponding entry in the address array 4 is read and the above control information is set in the third register 5. At this time, the block management information read out together with the control information is the content written in the block loading operation, and as a matter of course, the address comparator 6 selects the data read out from the buffer memory 2 from the microcontroller to be executed. It is determined that it is a command, and the state of flip-flop 7 is set to logical value 1. As a result, the flip-flop 7 instructs the decoder 8 that the data held in the second register 3 and the third register 5 are valid. The decoder 8 receives these, sends control signals to each control section inside the system, and calculates and executes the microinstructions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an apparatus for implementing the microprogram control method according to the present invention. 1, 3, 5...Register, 2...Buffer memory, 4...Address array, 6...Address comparator, 7...Flip-flop, 8...Decoder,
9...Large capacity memory.

Claims (1)

[Claims] 1. A first register for holding the address of a microinstruction, a buffer memory for temporarily storing a part of the microprogram in blocks, and a second register for holding the microinstruction read from the buffer memory. registers, block management information for the microprogram stored in the buffer memory, and control information commonly used for decoding microinstructions in the process of executing microinstructions in units of blocks. An address array having entries corresponding to each block of the buffer memory, a third register for holding the control information read from the address array, and a comparison between the contents of the first register and the block management information. a flip-flop for setting state 1 if said address comparator indicates a match and state 0 if said address comparator does not indicate a match; a decoder for decoding the contents of the second and third registers and outputting a control signal only when 1. A microprogram control system characterized in that it is realized by comprising a large capacity memory for storing a plurality of blocks and control information for each block held in the address array.