JPH0259727A - active matrix substrate - Google Patents
active matrix substrateInfo
- Publication number
- JPH0259727A JPH0259727A JP63211015A JP21101588A JPH0259727A JP H0259727 A JPH0259727 A JP H0259727A JP 63211015 A JP63211015 A JP 63211015A JP 21101588 A JP21101588 A JP 21101588A JP H0259727 A JPH0259727 A JP H0259727A
- Authority
- JP
- Japan
- Prior art keywords
- signal line
- active matrix
- metal film
- matrix substrate
- short
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、液晶表示パネルに用いられるアクティブマト
リックス基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an active matrix substrate used in a liquid crystal display panel.
従来の技術
近年、産業機器の小型化にともない従来からの表示装置
に代わる薄型平面表示装置が要望されている0種々ある
平面表示装置の中で液晶を用いた表示装置は、消費電力
が少なく、フルカラー表示が容易である点などから注目
されている。特に、表示画素の一つ一つにスイッチング
素子を設けたアクティブマトリックス型液晶表示パネル
は表示画質が優れているため携帯用のテレビなどに応用
されている。BACKGROUND OF THE INVENTION In recent years, with the miniaturization of industrial equipment, there has been a demand for thin flat display devices to replace conventional display devices.Among the various flat display devices, display devices using liquid crystals consume less power. It is attracting attention because it is easy to display in full color. In particular, active matrix liquid crystal display panels in which each display pixel is provided with a switching element have excellent display image quality and are therefore being applied to portable televisions and the like.
第4図は従来のアクティブマトリックス基板の構成を示
す等価回路図である。第4図において、51は薄膜トラ
ンジスタ、52は信号線をショート状態にするための金
属膜パターン、X1〜Xmは走査信号線、Yl−Ynは
映像信号線である。FIG. 4 is an equivalent circuit diagram showing the structure of a conventional active matrix substrate. In FIG. 4, 51 is a thin film transistor, 52 is a metal film pattern for shorting signal lines, X1 to Xm are scanning signal lines, and Yl-Yn are video signal lines.
ところが、アクティブマトリックス基板では、基板の製
造行程中に基板に帯電する静電気によってスイッチング
素子や走査信号線と映像信号線の交差部分の絶縁膜が破
壊され、ショート状態になってしまうという問題点があ
った。この静電気による絶縁膜の破壊防止対策として、
従来では第4図に示すようにアクティブマトリックス基
板の全ての端子を金属膜パターン52でショートしてお
く方法が用いられていた。また、特開昭61−4897
8号公報にみられるようにアクティブマトリックス基板
の走査信号線と映像信号線の片側だけをショートする方
法も提案されている。第5図にこの方法によるアクティ
ブマトリックス基板の構成図を示す。However, active matrix substrates have the problem that static electricity that builds up on the substrate during the manufacturing process destroys the insulation film at the intersections of switching elements and scanning signal lines and video signal lines, resulting in short circuits. Ta. As a measure to prevent damage to the insulating film due to static electricity,
Conventionally, a method has been used in which all terminals of an active matrix substrate are short-circuited with a metal film pattern 52, as shown in FIG. Also, JP-A-61-4897
As seen in Japanese Patent No. 8, a method has also been proposed in which only one side of the scanning signal line and video signal line of the active matrix substrate is short-circuited. FIG. 5 shows a block diagram of an active matrix substrate produced by this method.
発明が解決しようとする課題
しかしながら、第4図に示したような従来の静電気によ
る絶縁膜の破壊防止方法では、全ての端子がショートさ
れているためアクティブマトリックス基板の完成後、シ
ョート部分を切断するまで信号線の断線による断線欠陥
、隣合う走査信号線どうしゃ映像信号線どうしのショー
ト欠陥、走査信号線と映像信号線のショートといったシ
ョート欠陥を検査することはできなかった。また、第5
図に示す特開昭61−48978号公報による方法では
断線欠陥の検査は行なえるものの、やはり信号線のショ
ート部分を切断するまでは基板のショート欠陥の検査は
行えなかった。Problems to be Solved by the Invention However, in the conventional method for preventing breakdown of an insulating film due to static electricity as shown in Fig. 4, all terminals are short-circuited, so it is necessary to cut off the short-circuited parts after the active matrix substrate is completed. Until now, it was not possible to inspect short-circuit defects such as disconnection defects due to signal line disconnections, short-circuit defects between adjacent scanning signal lines or video signal lines, and short-circuits between scanning signal lines and video signal lines. Also, the fifth
Although the method disclosed in Japanese Patent Application Laid-Open No. 61-48978 shown in the figure can inspect for disconnection defects, it is impossible to inspect for short-circuit defects in the substrate until the short-circuit portion of the signal line is cut.
本発明はかかる点に鑑みてなされたもので、静電気によ
る絶縁膜の破壊を防止し、欠陥検査が行えるアクティブ
マトリックス基板を提供することを目的としている。The present invention has been made in view of these points, and an object of the present invention is to provide an active matrix substrate that prevents breakdown of an insulating film due to static electricity and allows defect inspection.
ti題を邂決するための手段
本発明は上記した課題を解決するために、アクティブマ
トリックス基板のスイッチング素子の走査信号線、映像
信号線を1本おきに複数本ずつガラス基板上に生成した
金属膜で接続し、かつ、信号線の入力端子の外側に形成
した共通電極パターンと複数本ずつ接続した信号線群を
半導体膜で接続するように構成したものである。Means for Solving the Problems The present invention solves the above-mentioned problems by using a metal film formed on a glass substrate for every other scanning signal line and video signal line of a switching element of an active matrix substrate. The semiconductor film is used to connect a plurality of signal lines to a common electrode pattern formed outside the input terminal of the signal line.
作用
本発明は上記した構成により、アクティブマトリックス
基板における静電気による絶縁膜の破壊を防止すると共
に、信号線の断線欠陥検査と複数本ずつ接続した走査信
号線群と映像信号線群間のショート欠陥検査を行うこと
を可能とする。Effect of the present invention With the above-described configuration, the present invention prevents breakdown of the insulating film due to static electricity on an active matrix substrate, and also inspects for disconnection of signal lines and short-circuit defects between a plurality of connected scanning signal line groups and video signal line groups. It is possible to do this.
実施例
以下、本発明の一実施例のアクティブマトリックス基板
について図面を参照しながら説明する。EXAMPLE Hereinafter, an active matrix substrate according to an example of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例におけるアクティブマトリッ
クス基板の構成図である。第1図において1は薄膜トラ
ンジスタ、2は走査信号線および映像信号線の入力端子
、3は走査信号線および映像信号線を複数本ずつショー
トするための金属膜パターン、4は信号線の入力端子の
外側に共通電極として金属膜で形成した共通電極パター
ン、5は信号線を複数本ずつショートさせた金属膜パタ
ーン3と共通電極パターン4を接続する半導体膜、X1
〜Xmは走査信号線、Y1〜Ynは映像信号線である0
本実施例では第1図に示すように走査信号線と映像信号
線は1本おきに金属膜パターン3に接続し、半導体膜5
を介して共通電極パターン4に接続されている。FIG. 1 is a configuration diagram of an active matrix substrate in one embodiment of the present invention. In FIG. 1, 1 is a thin film transistor, 2 is an input terminal for a scanning signal line and a video signal line, 3 is a metal film pattern for short-circuiting a plurality of scanning signal lines and video signal lines, and 4 is an input terminal for a signal line. A common electrode pattern formed of a metal film as a common electrode on the outside; 5 a semiconductor film connecting the metal film pattern 3 in which a plurality of signal lines are short-circuited and the common electrode pattern 4; X1;
~Xm is a scanning signal line, Y1~Yn is a video signal line 0
In this embodiment, as shown in FIG. 1, every other scanning signal line and video signal line is connected to the metal film pattern 3, and the semiconductor film 5
It is connected to the common electrode pattern 4 via.
第2図は金属膜パターン2と共通電極金属膜パターン3
を第1図のA部の構造図であり、第3図は第2図のa−
a’部における略断面図である。Figure 2 shows metal film pattern 2 and common electrode metal film pattern 3.
is a structural diagram of part A in Fig. 1, and Fig. 3 is a structural diagram of part A in Fig. 2.
FIG. 3 is a schematic cross-sectional view at section a'.
第2図、第3図で本実施例の構造を説明する。信号線の
入力端子2をガラス基板10上に形成するときに同時に
信号線をシv−トさせる金属膜パターン3も形成してお
く。次にスイッチング素子を形成するときに同時に金属
膜パターン3上に半導体膜5を形成する。そして、最後
に共通電極パターン4を信号線の補強膜とする金属膜1
2を形成するときに同時に形成する。半導体膜5は、数
Vの電圧を印加して行なう欠陥検査の時などには高い抵
抗値をもっているが、静電気によって数100〜数kV
の高電圧が信号線に加わった場合では十分低抵抗となっ
て静電気による電流を共通電極パターン4に流すことが
できる。The structure of this embodiment will be explained with reference to FIGS. 2 and 3. When forming the input terminal 2 of the signal line on the glass substrate 10, a metal film pattern 3 for shunting the signal line is also formed at the same time. Next, when forming a switching element, a semiconductor film 5 is formed on the metal film pattern 3 at the same time. Finally, the metal film 1 uses the common electrode pattern 4 as a reinforcing film for the signal line.
It is formed at the same time when forming 2. The semiconductor film 5 has a high resistance value when performing a defect inspection by applying a voltage of several volts, but it has a resistance value of several 100 to several kV due to static electricity.
When a high voltage of 2 is applied to the signal line, the resistance becomes sufficiently low and a current due to static electricity can flow through the common electrode pattern 4.
このように構成することでフォトマスクの枚数を増やす
ことなく静電気による絶縁膜破壊の防止対策を行うこと
ができる。また、第2図のb部で示す信号線と金属膜パ
ターン3の接続部分は検査終了後レーザ光線などで切断
しやすいように補強金属膜12を形成していない。With this configuration, it is possible to take measures to prevent insulation film breakdown due to static electricity without increasing the number of photomasks. In addition, the reinforcing metal film 12 is not formed at the connection portion between the signal line and the metal film pattern 3 shown in part b in FIG. 2 so that it can be easily cut with a laser beam or the like after the inspection is completed.
次に本実施例による欠陥検査方法について説明する。信
号線の断線検査は、走査信号線、映像信号線とも片側の
端子は接続されていないので、金属膜パターン3と入力
端子210−ブ針を接続し、抵抗値を測定することで検
査することができる。Next, a defect inspection method according to this embodiment will be explained. To test for disconnection of the signal line, since the terminals on one side of both the scanning signal line and the video signal line are not connected, the inspection can be performed by connecting the metal film pattern 3 and the input terminal 210-b needle and measuring the resistance value. Can be done.
隣合う信号線どうしのショート欠陥検査は信号線が1本
おきに金属膜パターン3に接続されているため金属膜パ
ターン3にプローブ針を接続し、抵抗値を測定すること
で当該ブロックの中でのショート欠陥検査を行うことが
できる。また、走査信号線と映像信号線間のショート欠
陥検査は、各々の金属膜パターン3は半導体膜5を介し
て接続しているので電気的に十分高抵抗であり、走査信
号線側の金属膜パターンと映像信号線側の金属膜パター
ンにプローブ針を接続し、抵抗値を測定することで当該
ブロックの中でのショート欠陥検査を行うことができる
。To inspect for short defects between adjacent signal lines, every other signal line is connected to the metal film pattern 3, so by connecting a probe needle to the metal film pattern 3 and measuring the resistance value, it is possible to detect short defects in the block. Short defect inspection can be performed. In addition, when inspecting for short defects between the scanning signal line and the video signal line, since each metal film pattern 3 is connected via the semiconductor film 5, the electrical resistance is sufficiently high, and the metal film on the scanning signal line side By connecting a probe needle to the pattern and the metal film pattern on the video signal line side and measuring the resistance value, short-circuit defects in the block can be inspected.
発明の効果
以上の説明のように本発明は、アクティブマトリックス
基板のスイッチング素子の信号線を一本おきに複数本ず
つガラス基板上に生成した金属膜で接続し、かつ、信号
線の入力端子の外側に形成した金属膜のパターンと前記
複数本ずつ接続した信号線群を半導体膜で接続すること
で、静電気による絶縁膜破壊の保護を行うと共に、走査
信号線、映像信号線の断線欠陥検査やショート欠陥検査
を行うことが可能であるというすぐれた効果を有する。Effects of the Invention As explained above, the present invention connects every other signal line of a switching element of an active matrix substrate with a metal film formed on a glass substrate, and By connecting the metal film pattern formed on the outside and the group of connected signal lines with a semiconductor film, it is possible to protect the insulation film from breakdown due to static electricity, and also to inspect for disconnection defects in scanning signal lines and video signal lines. This has an excellent effect in that short defect inspection can be performed.
第1図は本発明の一実施例におけるアクティブマトリッ
クス基板の構成図、第2図は第1図のA部の構造図、第
3図は第2図のa−a″部における略断面図、第4図、
第5図は従来のアクティブマトリックス基板の構成を示
す構成図である。
1・・・・・・薄膜トランジスタ、2・・・・・・入力
端子、3・・・・・・金属膜パターン、4・・・・・・
共通電極パターン、5・・・・・・半導体膜、x1〜X
m・・・・・・走査信号線、Y1〜Yn・・・・・・映
像信号線。
代理人の氏名 弁理士 粟野重孝 はか1名3− 金属
膜パターン
4− 共通を極バターシ
5−半導#膳
第
図
第
図FIG. 1 is a configuration diagram of an active matrix substrate according to an embodiment of the present invention, FIG. 2 is a structural diagram of section A in FIG. 1, and FIG. 3 is a schematic sectional view taken along section a-a'' in FIG. Figure 4,
FIG. 5 is a block diagram showing the structure of a conventional active matrix substrate. 1... Thin film transistor, 2... Input terminal, 3... Metal film pattern, 4...
Common electrode pattern, 5... Semiconductor film, x1-X
m...Scanning signal line, Y1-Yn...Video signal line. Name of agent: Patent attorney Shigetaka Awano 1 person 3- Metal film pattern 4- Common pattern 5- Semiconductor #Zen diagram Figure
Claims (3)
状に配置したアクティブマトリックス基板であって、前
記スイッチング素子の信号線を1本おきに複数本ずつ前
記ガラス基板上に生成した金属膜で接続し、かつ、前記
信号線の入力端子の外側に形成した金属膜のパターンと
前記複数本ずつ接続した信号線群を半導体膜で接続して
いることを特徴とするアクティブマトリックス基板。(1) An active matrix substrate in which switching elements are arranged in a matrix on a glass substrate, wherein every other signal line of the switching elements is connected by a metal film formed on the glass substrate, and . An active matrix substrate, characterized in that a metal film pattern formed on the outside of the input terminal of the signal line and the plurality of connected signal lines are connected by a semiconductor film.
ーンは、前記信号線のパターン幅より十分太くして共通
電極としたことを特徴とする請求項(1)記載のアクテ
ィブマトリックス基板。(2) The active matrix substrate according to claim 1, wherein the metal film pattern formed outside the input terminal of the signal line is sufficiently thicker than the pattern width of the signal line to serve as a common electrode.
トランジスタで構成されていることを特徴とする請求項
(1)記載のアクティブマトリックス基板。(3) The active matrix substrate according to claim (1), wherein the switching element is composed of a two-terminal element or a thin film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21101588A JPH0711641B2 (en) | 1988-08-25 | 1988-08-25 | Active matrix substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21101588A JPH0711641B2 (en) | 1988-08-25 | 1988-08-25 | Active matrix substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0259727A true JPH0259727A (en) | 1990-02-28 |
| JPH0711641B2 JPH0711641B2 (en) | 1995-02-08 |
Family
ID=16598931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21101588A Expired - Fee Related JPH0711641B2 (en) | 1988-08-25 | 1988-08-25 | Active matrix substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0711641B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0268522A (en) * | 1988-09-02 | 1990-03-08 | Matsushita Electric Ind Co Ltd | active matrix substrate |
| JPH06337438A (en) * | 1993-05-31 | 1994-12-06 | Nec Corp | Liquid crystal display device and manufacture thereof |
| NL9400925A (en) * | 1993-06-11 | 1995-01-02 | Sharp Kk | Inspection device and inspection method for display device. |
| JP2006126619A (en) * | 2004-10-29 | 2006-05-18 | Toshiba Matsushita Display Technology Co Ltd | Display apparatus |
| JPWO2007055047A1 (en) * | 2005-11-10 | 2009-04-30 | シャープ株式会社 | Display device and electronic device including the same |
-
1988
- 1988-08-25 JP JP21101588A patent/JPH0711641B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0268522A (en) * | 1988-09-02 | 1990-03-08 | Matsushita Electric Ind Co Ltd | active matrix substrate |
| JPH06337438A (en) * | 1993-05-31 | 1994-12-06 | Nec Corp | Liquid crystal display device and manufacture thereof |
| NL9400925A (en) * | 1993-06-11 | 1995-01-02 | Sharp Kk | Inspection device and inspection method for display device. |
| US5473261A (en) * | 1993-06-11 | 1995-12-05 | Sharp Kabushiki Kaisha | Inspection apparatus and method for display device |
| JP2006126619A (en) * | 2004-10-29 | 2006-05-18 | Toshiba Matsushita Display Technology Co Ltd | Display apparatus |
| JPWO2007055047A1 (en) * | 2005-11-10 | 2009-04-30 | シャープ株式会社 | Display device and electronic device including the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0711641B2 (en) | 1995-02-08 |
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