JPH0260219B2 - - Google Patents

Description

[Detailed description of the invention]

[Summary] The contact area between the cap layer on the two-dimensional electron gas (hereinafter abbreviated as 2DEG) supply layer and the gate electrode is reduced with good reproducibility to reduce the gate capacitance C _g without increasing the source resistance R _s . , and improve gate breakdown voltage. [Industrial Application Field] The present invention relates to a recessed heterojunction field effect transistor (FET) in which the contact area between a gate electrode and a cap layer is reduced. Heterojunction FET is a high-speed device that uses high-mobility 2DEG generated at the heterojunction interface as a carrier. Heterojunction FETs often have a recess structure in which the threshold voltage V _th is determined by the depth of recess etching of the cap layer. In a recessed structure, when the sidewalls of the cap layer and the gate electrode come into contact, the gate capacitance increases and the gate breakdown voltage decreases, so a structure in which a portion of the cap layer around the gate is removed in the thickness direction has been proposed. However, reproducibility of removal is difficult. [Prior Art] FIG. 3 is a sectional view of a conventional heterojunction FET. In the figure, 1 is semi-insulating gallium arsenide (SI-
GaAs) substrate, on which intrinsic gallium arsenide (i-
GaAs) layer 2, n-type aluminum gallium arsenide (n-AlGaAs) layer 3 as the 2DEG supply layer, and n-type gallium arsenide (n-AlGaAs) layer 3 as the cap layer.
GaAs) layers 4 are sequentially grown, and the n-GaAs layer 4 in the gate forming portion is removed (recess etching) to form a gate electrode 7 made of aluminum (Al). Recess etching is performed by anisotropic reactive ion etching (RIE) using CCl ₂ F ₂ as an etchant. Before forming the gate electrode 7, ohmic (source, drain) electrodes 8, 9 made of gold germanium/gold (AuGe/Au) are formed so as to reach the i-GaAs layer 2. In the FET with this structure, the sidewall of the gate electrode 7 contacts the sidewall of the n-GaAs layer 4 of the cap layer, and a parasitic gate capacitance C _g ' is generated at this contact surface.
In addition, the gate breakdown voltage decreases. Figure 4 shows an improved conventional heterojunction FET.
FIG. In this case, prior to the RIE of recess etching, the n-GaAs layer 4 of the cap layer is side-etched by isotropic etching using HF as an etchant, and the side walls of the gate electrode 7 and the n-GaAs layer 4 of the cap layer are side-etched.
- The contact area with the sidewall of the GaAs layer 4 is reduced. However, since wet etching is performed without selectivity in this case, there are problems with process reproducibility, and if the etching depth is too large, not only will the source resistance R _s increase, but the threshold voltage is out of control. Furthermore, if the etching depth is too small, the gate capacitance C _g will increase. [Problems to be Solved by the Invention] In conventional heterojunction FETs in which the area around the gate of the cap layer is side-etched, there is a problem in the reproducibility of recess etching, which tends to cause deterioration of characteristics. [Means for solving the problem] The above problem is solved by forming an intrinsic gallium arsenide layer 2 as a 2DEG generation layer and a first n-type aluminum gallium arsenide layer as a 2DEG supply layer on a semi-insulating gallium arsenide substrate 1. 3. A first n-type gallium arsenide layer 4 as a first cap layer, a second n-type aluminum gallium arsenide layer 5 as an etching stop layer, and a second n-type gallium arsenide layer 6 as a second cap layer in this order. After growing and removing the second n-type gallium arsenide layer 6 in the gate formation region wider than the gate formation region using isotropic etching, the gate is etched using anisotropic etching predominant in the direction perpendicular to the substrate. The second aluminum gallium arsenide layer 5 in the formation region
and removing the first n-type gallium arsenide layer 4,
A gate electrode 7 is formed on the exposed first n-type aluminum gallium arsenide layer 3;
This is achieved by the heterojunction field effect transistor according to the present invention, in which ohmic electrodes 8 and 9 are formed on both sides of the gate electrode 7 so as to reach the intrinsic gallium arsenide layer 2. [Function] In order to obtain a heterojunction FET with small source resistance R _s and parasitic gate capacitance C _g ', the present invention provides an n-AlGaAs layer as an etching stopper layer in the n-GaAs layer of the cap layer. Using a cap layer with a layered structure, when recess etching the gate forming area, firstly, the n-GaAs layer is etched up to this n-AlGaAs layer.
This proposed a layer structure that can improve process reproducibility by performing isotropic selective etching on the 2DEG supply layer, followed by anisotropic selective etching up to the n-AlGaAs layer of the 2DEG supply layer. [Example] FIG. 1 is a sectional view of a heterojunction FET of the present invention. In the figure, 1 is the SI-GaAs substrate, on which
i-GaAs layer 2 with a thickness of 1000 Å as a 2DEG generation layer,
A 400 Å thick n-AlGaAs layer 3 as a 2DEG supply layer, a 150 Å thick first n-GaAs layer 4 as a first cap layer, and a 50 Å thick second n-GaAs layer 4 as an etch stop layer.
AlGaAs layer 5, a second n layer with a thickness of 300 Å as a second cap layer
- Sequentially grow GaAs layers 6. The n-type layer is formed by doping silicon (Si), and the carrier concentration of each layer is 1×10 ¹⁸ cm ⁻³ . Next, the n-GaAs layer 6 and the n-
AlGaAs layer 5 and n-GaAs layer 4 are removed to form gate electrode 7 made of Al. In this case, the n-GaAs layer 6 is side-etched so as not to contact the gate electrode. Before forming the gate electrode 7, ohmic electrodes 8 and 9 made of AuGe/Au are formed so as to reach the i-GaAs layer 2. In this structure, the 2DEG supply layer n-
n-GaAs layer 4 on AlGaAs layer 3 and n-
The thickness of the AlGaAs layer 5 is 150 and 50 Å, and the 2DEG has sufficient electron density due to this thickness, so
The source resistance R _s does not increase. Moreover, the thickness of the gate electrode in contact with the side wall is 200 Å, and the parasitic gate capacitance C _g ′ is small. Next, an outline of the process for producing an FET with this structure will be explained. In FIG. 2, 1 to 3 are cross-sectional views illustrating the manufacturing process of the heterojunction FET of the present invention. In FIG. 2, in step 1, ohmic electrodes 8 and 9 of AuGe/Au (200/2800 Å) are deposited and alloyed on the surface of the same layer structure as in FIG. 1 by molecular beam epitaxial growth (MBE) or the like. Next, a photoresistor 11 is applied, a gate formation region is opened, and n-etching is performed using a wet etching method using H ₂ O ₂ and NH ₄ OH as an etchant.
The n-GaAs layer 6 is selected from the AlGaAs layer 5 and isotropically etched. This isotropic etching may be performed by RIE using CCl ₂ F ₂ as an etchant at a pressure of 30 Pa. In this isotropic etching, the progress of etching in the depth direction is prevented by the n-AlGaAs layer 5 as an etching stopper layer, so that the source resistance R _s does not increase due to overetching. In _FIG . ₂ , the n-AlGaAs layer 5 and the n-
The GaAs layer 4 is anisotropically etched predominantly in the direction perpendicular to the substrate to expose the n-AlGaAs layer 3. In Figure 2 and 3, Al was deposited to a thickness of 4000 Å,
Gate electrode 7 is formed, and Al other than gate electrode 7 is
The layer is lifted off along with the photoresist 11 and removed. [Effects of the Invention] As explained in detail above, in the heterojunction FET in which the cap layer around the gate is side-etched according to the present invention, the reproducibility of recess etching is good, and the parasitic gate capacitance is reduced without increasing the source resistance _Rs . Reduce C _g ′ and improve gate breakdown voltage.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the heterojunction FET of the present invention.
In Fig. 2, 1 to 3 are cross-sectional views explaining the manufacturing process of the heterojunction FET of the present invention, Fig. 3 is a cross-sectional view of a conventional heterojunction FET, and Fig. 4 is a cross-sectional view of an improved conventional heterojunction FET. FIG. In the figure, 1 is SI-GaAs substrate, 2 is 2DEG
The i-GaAs layer is the generation layer, and the n-GaAs layer is the 2DEG supply layer.
AlGaAs layer 4 is the first cap layer and the first n-
GaAs layer, 5 is an etching stopper layer and the second n-
AlGaAs layer 6 is the second cap layer and the second n-
GaAs layer, 7 is a gate electrode made of Al, 8 and 9 are
This is an ohmic electrode made of AuGe/Au.

Claims (1)

[Claims] 1. On a semi-insulating gallium arsenide substrate 1, an intrinsic gallium arsenide layer 2, a first n-type aluminum gallium arsenide layer 3, a first n-type gallium arsenide layer 4, a second n-type aluminum After sequentially growing a gallium arsenide layer 5 and a second n-type gallium arsenide layer 6, and removing the second n-type gallium arsenide layer 6 in the gate formation region wider than the gate formation region, the second n-type gallium arsenide layer 6 in the gate formation region is removed. removing the n-type aluminum gallium arsenide layer 5 and the first n-type gallium arsenide layer 4; forming a gate electrode 7 on the exposed first n-type aluminum gallium arsenide layer 3; A heterojunction field effect transistor characterized in that ohmic electrodes 8 and 9 are formed on both sides apart from the gate electrode 7 so as to reach the intrinsic gallium arsenide layer 2.