JPH0260291A - descrambling device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention receives a broadcast signal including a video signal scrambled by an intra-scanning line signal switching method (hereinafter referred to as line rotation method), and converts the scrambled video signal. The present invention relates to a descrambling device that descrambles and obtains a normal video signal.

2. Description of the Related Art Conventionally, a descrambler for descrambling a video signal scrambled by a line rotation method and for obtaining a normal video signal is constructed as shown in FIG.

In FIG. 4, 1 is a video data node, into which a video signal scrambled using the line rotation method is input. 2 is a changeover switch, which switches for each horizontal line, and the data node 1 and line memory 3a, 3b is alternately connected to output the scrambled video signal to the line memories 3a and 3b.4.
is a flip-flop serving as a clock means, which divides the frequency of the horizontal pulse HP by two to generate a reference clock for controlling the on/off of each switch and the timing of reading and writing of the memory for each horizontal line. Reference numeral 5 designates an address counter which is reset by a horizontal pulse Hp and whose output is always connected to the writing side line memories 3a and 3b by a switch 6 switched by the output of the flip-flop 4. 7 is a preset address counter in which a cutting point address value DA, which is descrambling information, is preset for each horizontal line in synchronization with the horizontal pulse HP. The output of the preset address counter 7 is constantly supplied to the line memories 3a and 3b on the read side by a switch 6. 8 is a second selector switch, which is a switch for outputting the video signal read from the line memories 3a and 3b, and is always differentially connected to switch 2, and is connected to the line memory on the write side to which switch 2 is connected. 1J3a.

It is connected to line memories 3a and ab on the opposite side of line memory 3b, that is, on the read side. Reference numeral 9 denotes an output bus to which the descrambled video signal is output.

The operation of the conventional descrambler configured as described above will be described below. The scrambled video signal is sent from the data bus 1 through the switch 2 to either the line memory 3a or 3b at the beginning of the memory address. 11 horizontal lines are written, and in the next line, as the switch 2 is switched in synchronization with the clock CLK, the other line memories 3a and 3b are switched and a similar video signal is written. Writing into the line memories 3a and 3b is performed by energizing the address information output from the address counter 6, and the scrambled video signal for one horizontal line is written into the line memories 3a and 3b.
The data is sequentially written to each address within 3b. The preset address counter 7 is preset with cutting point address information DA of the scrambled video signal of a certain horizontal line written in the line memories 3a and 3b, and this cutting point address information DA is synchronized with the clock CLK. It is sent to the line memories 3a and 3b on the read side. The line memories 3a and sb into which the scrambled video signal has been written receive the video signal from the cut point address indicated by the cut point address information sent from the precent address counter 7 in synchronization with the CLK. Start reading,
After reaching the final address of the line memories 3a, 3b, the process returns to the top address and sequentially reads out the video signal up to just before the cutting point address. In this way, the video signal is descrambled and output via the data bus 9.

In parallel with the descrambling process in one line memory described above, the scrambled input video signal is written to the other line memory.

By repeating the above operations, a descrambled video signal is output from the data bus 9.

Problems to be Solved by the Invention According to the configuration of the conventional descrambler described above, as is clear from FIG. 2, two line memories and two address counters are required to descramble the scrambled video signal. becomes. Since two sets of line memories and address counters are required to be reduced at the minimum in this way, reduction in component costs is hindered, making it impossible to provide a descrambling device at a low cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a descrambling device that descrambles a line rotation scrambled video signal using one line memory in the same way as a conventional descrambling device.

Means for Solving the Problems In order to achieve the above object, the descrambling device of the present invention has a descrambling device in which a signal at a cutting point portion of a scrambled video signal one horizontal line before in a previously written line memory is written. Using the read-modify-write method, the newly input scrambled video signal is read from the previous address by one horizontal line, and the newly input video signal is input to the empty address. It's something to write down.

Effect According to the above configuration, by constantly read-modifying-write to the line memory, it becomes possible to descramble the video signal that has been scrambled using the intra-scanning line signal switching method, and one line memory is used as the line memory. Accordingly, descrambling processing similar to that using a conventional 2-line memory 1/2 address counter can be realized.

As a result, it becomes possible to reduce the number of line memories and address counters used, and it becomes possible to provide an inexpensive descrambling device with a simple configuration.

Embodiment Hereinafter, an embodiment of the descrambling apparatus of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a descrambler according to an embodiment of the present invention. 1st
In the figure, 10 is a line memory, into which a video signal scrambled using the line rotation scrambling method among the broadcast signals sent from the transmitting side using the CATV transmission method is input, written for each horizontal line, and then descrambled. It is read out so that a video signal obtained by 11 is a first adder; one input receives descrambling information sent from the transmitting side along with the broadcast signal, that is, cutting address information DA for each horizontal line, and the other input receives descrambling information sent from the transmitting side together with the broadcast signal, and the other input receives descrambling information sent from the transmitting side together with the broadcast signal, and the other input receives descrambling information sent from the transmitting side together with the broadcast signal; ) Address information DAP indicating previous disconnection address information is input. 12 is a first remainder calculator which calculates the maximum address D of the line memory 10 so that the added value of the address information DA and DAP added by the adder 11 does not exceed the data amount for one horizontal line.
Obtain the remainder for MAX. A flip-flop 13 receives the output of the remainder calculator 12 and outputs address information DAP to the adder 11 in synchronization with the horizontal pulse Hp. 14 is an address counter, which uses the horizontal pulse HP as a reset pulse serving as a reference pulse for driving, and converts from the minimum address information processing N (address o) to the maximum address DMA in a 1H period.
Count up to X repeatedly. The outputs of the remainder calculator 12 and the address counter 14 are both input to the second adder 15, and the added value is output to the second remainder calculator 16. Then, the remainder value for the maximum address DMAX in the remainder calculator 16 is inputted to the line memory 10 as a read modify address asset. In the line memory 10, the previously stored scrambled video signal for one horizontal line is read out according to the read modification address DRM, and the newly input scrambled video signal for one horizontal line is read out according to the read modification address DRM. Write in order. That is, sequential information is written to an address that becomes an empty area as a result of completion of reading from an address.

The operation of the descrambling device constructed as described above will be explained below with reference to FIGS. 2 and 3. Here, the address of the line memory 10 will be explained assuming that the maximum address DMAX=1QO is from address 0 to address 99. Therefore, the address counter 14 counts the horizontal pulse HP from 0' to 99'' as a reset pulse.The respective data needed to explain the descrambling will be explained below using the values shown in FIG.

Now, the output of the remainder calculator 12 2H ago is "90", and 1
Since the cutting point address of the video signal before H is "2o", DA = "20" and DAP = "90" in the B period, and as a result, the output of the adder 11 is "110", and the remainder calculator 12 output becomes "10".Next, address counter 1
The result of adding 4 outputs and the output of the remainder calculator 12 in the adder 15 is +101112. ..., 109", and the output of the remainder calculator 16, that is, the read modify address is "10, 11, 12. ..., 99
.

9".According to this read modify address, the scrambled video signal from 1H before is read out from the cutting point. Information is read out in conjunction with the reading of the video signal from 1H before. The scrambled video signal shown in FIG. 2 (-) is written into the vacant address from the beginning.

Now, the cutting point address for this period is "40",
This DA="4o" and the output DAP of the flip 70 knob 13 indicating the output content of the remainder calculator 12 1H period ago =
“1o” is input to the addition 17% 11ic and added. Addition result address in this adder 11 = “6
0'' is input to the remainder calculator 12, and the remainder calculation result and the count output of the address counter 14 are input to the adder 15 and added.The addition results are 60, 51,
62°..., 148, 149". The remainder of this addition result with respect to the maximum address DMAX="100" is calculated by the remainder calculator 16, and the read modifier L/S is "50, 51". ．．・−・−,9901・・
..., 48.49'' is obtained.

As a result, the video signal with the cut point address = "40" shown in FIG. 2(a) during the C period is
Read from address “60” of 0, address “99”,”
The scrambled video signal of the cutting point address - "40" written from the address "10" of the line memory 10 at the time of writing is read out through the address "Q" to the final address "49". The data is read from address 60” to address 49 in one round, and the second address is read out.
The signal is descrambled and obtained as the output of the line memory 1010 as shown in FIG.

As described above, according to this embodiment, it is possible to descramble a video signal that has been subjected to line rotation scrambling using one line memory and one address counter.
Compared to the one using 2 address counters, equivalent descrambling processing can be achieved with a configuration with one fewer set of line memory and address counters, simplifying the circuit and reducing component costs, resulting in an inexpensive descrambling device. It becomes possible to provide

Effects of the Invention According to the present invention, the video signal scrambled by the intra-scanning transfer method can be decoded by read-modifying-write the video signal scrambled by the intra-scanning transfer method to one line memory. An inexpensive descrambling device with a simple configuration that uses a 1-line memory as its main component while maintaining the same descrambling processing function as a conventional 2-line memory that switches read/write at a disconnection point for scrambling. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a descrambling device according to an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams and timing charts for explaining the operation of the descrambling device, and FIG. 4 is a diagram of a conventional example. FIG. 2 is a block diagram of a descrambling device. 10...Line memory, 11.15...
・Adder, 12.16... Remainder calculator, 14.
...Address counter. Name of agent: Patent attorney Shigetaka Awano (1 person)

Claims (1)

[Claims] A line memory capable of writing/reading one horizontal line component of a video signal scrambled by an intra-scanning line signal switching method, and a control means for controlling writing/reading of the line memory, and the control means is configured to cutting point information for each horizontal line is input, and the video signal of the first horizontal line stored in the line memory is cycled from the address indicating the cutting point of the video signal of the first horizontal line. At the same time as reading the line memory, reading the video signal of the first horizontal line and writing the scrambled video signal of the second horizontal line following the first horizontal line to the address that becomes an empty area. A descrambling device characterized in that read modify address information is output to the line memory.