JPH0260318A - Driving circuit for insulated gate type semiconductor for electric power - Google Patents

Abstract

PURPOSE:To prevent the heat runaway of a switching semiconductor for control used for the driving of a pulse transformer and to improve the reliability by providing a monostable multivibrator, a high band filter, an inverter and an AND gate. CONSTITUTION:An AND gate 14 is turned on only during the ON control period of a control signal inputted from an input terminal 2. By a switching control signal outputted from a monostable multivibrator 15 during the ON control period, an FET7 as a switching element for control is switched. At this time, each time the FET7 is turned off, the voltage of the connecting point of the primary winding and the FET7 of a pulse transformer 5 is reduced from the peak value immediately after OFF to a threshold value by the action of an inverter 13 based on the output signal of a high band filter 12, and thereafter, a vibrator 15 is triggered. Thus, the turning ON of the FET7 is executed after the voltage lower than the peak value is obtained, the heat loss of the FET 7 is reduced and the heat runaway is prevented and therefore, the reliability can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drive circuit for an insulated gate type power semiconductor such as a power MOSFET or CB used as a switching element of a switching power supply device.

[Conventional technology]

Conventionally, as shown in FIG. 3, a drive circuit for an insulated gate power semiconductor ≠≠ includes a signal processing circuit that outputs a control signal for controlling the on/off of the semiconductor e and the semiconductor Φ.
≠ and are isolated using a pulse transformer.

Figure 3 shows a power M as an insulated gate power semiconductor e.
The drive circuit of O5FET (1) is shown, and in the same figure,
(2) is the input terminal for the on/off control signal of FET (1), (3) is an oscillation circuit that oscillates at several MHz, which is sufficiently higher than the switching frequency of FET (1), and (4) is the control signal and oscillation circuit. This is an AND gate to which the output signal of (3) is input, and is turned on by a high-level control signal during the on-control period Ton.

(5) is an insulating pulse transformer with a winding ratio of 1:1, and one end of the beginning of the primary winding (5a) is connected to a DC power source (6) with a positive voltage Vc. (7) is a small signal MO5FET forming a control switching element, whose drain is connected to the other end of the primary winding (5a), whose t and source are grounded, and whose gate C and AND gate are connected to the other end of the primary winding (5a). (
The output signal of 4) is applied.

(8) and (9) are the secondary winding (5b) of the transformer (5).
) are connected in series between one end of the beginning of the winding and the gate of FET (1), QO is a PNP type transistor that forms a switching semiconductor for the discharge path, and the base is a diode (8). , (9), and the emitters are diode (9) and FET (
1), and the collector is connected to the connection point of the gate of 2.
It is connected to the other end of the next winding (5b). Ql) is a bias resistor provided between the base and collector of the transistor QO.

Note that the other end of the secondary winding (5b) is connected to the source of the FET (1).

Then, the control signal is transmitted to the FET as shown in FIG. 4(a).
It becomes high level during the on control period Ton of FET (1), and becomes low level during the off control period Toff of FET (1).

On the other hand, the oscillation circuit (3) is as shown in FIG. 4(b).
Outputs an oscillation signal with a constant frequency of several MHz.

Based on the high level of the control signal, the AND gate (4) is turned on only during the on control period Ton, and during that period,
As shown in FIG. 4(C), the output signal of the oscillation circuit (3) is applied to the gate of the FET (7), and the FET (7) switches at the frequency of the output signal of the oscillation circuit (3).

Furthermore, based on the switching of FET (7), 1
A DC power supply (6) is intermittently applied to the next winding (5a),
The transformer (5) is pulse driven and the secondary winding m (5b)
A pulse of gate control power for FET (1) is generated.

Then, the output pulse of the secondary winding (5b) is transmitted through the diode (
8 is applied to the gate of FET (1) through (9), and at this time, the output pulse interval is shorter than the off-to-on recovery period of transistor QO, so that transistor (10) is kept off. Moreover, since the pulse is integrally charged and smoothed by the capacitance Cgs between the gate and source of FET (1), the gate voltage of FET (1) remains almost constant as shown in Fig. 4(d). The on-state voltage is maintained, and the FET (1) is kept on-state.

Next, from the on control period Ton to the off control period Toff
At time fζ at t1 in FIG. 4(a), the transistor 0Q is switched from off to on based on the cutoff of the output pulse of the secondary winding (5b), and the accumulated charge in the capacitor Cgs is transferred via the transistor C1O. FET (1) quickly flips off.

After that, the same operation as described above is repeated based on the level inversion of the control signal, and the frequency of the control signal is changed.

For example, FET (1) switches at about 100 KHz.

[Problems to be Solved by the Invention] In the drive circuit shown in FIG. 3, the voltage Vc of the power supply (6)
When is set to 15V, the oscillation circuit (3) shown in Figure 5←)
1 when FET (7) is turned off by the output signal of )
The voltage at the connection point between the next winding (5a) and the FET (7), that is, the drain-source voltage Vds of the FET (7) is:
Based on the back electromotive voltage of the inductance of the transformer (5), its peak value reaches approximately 40V, which is more than twice the voltage Vc, as shown in FIG.

Since the oscillation circuit (3) operates at a constant frequency regardless of the operation of the FET (7), etc., when the voltage Vds is approximately at the peak value, the rise of the output signal of the oscillation circuit (3) causes F E A situation may also occur in which T (7) is turned on, and in this case, it is charged with the voltage of the peak value.
, : Drenino of FET (7), Cd between sources
A large stored energy (=-Ccls Vds) of s is consumed in the FET (7), and the heat loss of the FET (7) becomes large, causing the temperature of the FET (7) to become extremely low.

Therefore, there is a problem that the FET (7) is easily damaged due to thermal runaway, and reliability cannot be improved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable insulated gate power semiconductor drive circuit that prevents thermal runaway of a control switching semiconductor used to drive a pulse transformer.

[Top means to solve problems]

In order to achieve the stated purpose, in the insulated gate type power semiconductor drive circuit of the present invention, the ON control period of the power semiconductor is controlled based on a control signal for turning on and off the insulated gate type IE power semiconductor. Then, the control switching semiconductor connected in series to the primary winding of the insulating pulse transformer is driven at high frequency, and the output pulse of the secondary winding of the pulse transformer described in J is applied to the gate of the main semiconductor in Article 11. death,
Discharge path switching that holds the power semiconductor on by integral charging of the inter-terminal capacitance of the power semiconductor, and turns on by cutting off the output pulse when switching to off control where the output pulse is cut off. discharging the accumulated charge in the inter-terminal capacitance of the power semiconductor by the semiconductor;
In the drive circuit for an insulated gate power semiconductor that turns off the power semiconductor, the input of the control signal causes the AND gate to turn on during the ON control period, and the rise of the output signal of the AND gate. a monostable multivibrator that is triggered and supplies a switching control signal with a minute pulse width for high-frequency driving to the switching semiconductor PC; and a voltage at a connection point between the primary winding and the switching semiconductor, which is based on switching of the switching semiconductor. a high-pass filter that extracts high-frequency fluctuations in the TJ filter, and the output signal of the TJ filter is binarized and inverted at a threshold for detecting a drop in off-voltage, and the voltage at the connection point is lowered by the threshold value p. A technical measure is taken to include an inverter that outputs a trigger signal that sometimes rises to the AND gate.

[Effect]

In the insulated gate power semiconductor drive circuit configured as described above, the control switching semiconductor is switched by the switching control signal output from the monostable multivibrator during the on-control period, and at this time, the control switching semiconductor is switched by the switching control signal output from the monostable multivibrator. Every time the semiconductor turns off, the inverter operates based on the output signal of the high-pass filter.
After the voltage at the connection point between the primary winding of the pulse transformer and the control switching semiconductor drops from the peak value immediately after turning off to the threshold value, the monostable multivibrator is activated, so the control switching semiconductor Turn-on is performed after the voltage becomes lower than the iJ peak value, thereby reducing heat loss of the control switching semiconductor and preventing thermal runaway.

〔Example〕

One embodiment will be described below with reference to FIGS. 1 and 2.

Figure 1 (here, the same symbols as in Figure 3 indicate the same things, 02 is formed by connecting a capacitor (12a) and a resistor (12b) in series between the drain of the FET (7) and the ground) The input terminal of the high-pass filter q] is a resistor α3)'
The inverter (3.4) is connected to the connection point of the capacitor (12a) and resistor (12+) through the input terminal (3.4).
It is a monostable multivibrator that is triggered by the rise of the output signal of Q4), which is an AND gate into which the control signal of 2) and the output signal of the inverter are input. A switching control signal with a minute pulse width for high frequency driving is supplied to the gate of the FET (7) forming a semiconductor.

Then, as shown in FIG. 2(a), when the control signal becomes high level at time ta and transitions to the on-control period Ton,
The AND gate 04) is turned on/off by the high level of the control signal.

At this time, the FET (7) is turned off and the voltage at the connection point between the primary winding (5a) and the FET (7), that is, the FET (7)
The drain-source voltage Vcls of is shown in Figure 2 (+))
+ As shown, the capacitor (1
2a), the voltage at the connection point of the resistor (12b), that is, the voltage of the output signal of the filter α2, is maintained at 0■ as shown in FIG. 2(C).

In addition, the input threshold of the inverter so, which forms the threshold for detecting a drop in the off-voltage, is set to Ov, and the inverter α
The voltage of the output signal is maintained at a high level as shown in FIG. 2(d).

Therefore, when the control signal rises to high level, the output signal along AND gate α rises to high level, multivibrator αθ is triggered, and multivibrator 09
to the gate of FET (7), for example, LOOnse(
A high-level switching control signal with a minute pulse width of
, current from the power supply (6) flows through the FET (7).

At this time, the voltage of the output signal of the filter α decreases to the voltage -Vc as shown in FIG.

Next, the switching control N of the multivibrator 0θ
When the signal falls to a low level and the FET (7) turns off, the primary winding (5a) is cut off and the transformer (5) is turned off.
The high voltage based on the back electromotive force of the inductor Junos is FE.
T(7), the voltage Vds transiently becomes a high voltage more than twice the voltage Vc, and then, due to the disappearance of the back electromotive voltage, the voltage Vds begins to decrease to -pVc, and the voltage Vd
s fluctuates at high frequencies as shown in FIG. 2(b).

At this time, the capacitor (12a) is charged and discharged according to the fluctuation of the voltage Vcls, the high frequency fluctuation of the voltage Vds is extracted by the filter (12), and the output signal of the filter α changes to follow the fluctuation of the voltage Vds.

When the voltage Vds decreases to Vc, the voltage of the output signal of the filter α2 decreases to OV of the input threshold of the inverter (13), and the output signal of the inverter σ, which forms the trigger signal, becomes As shown in FIG. 2(d), it rises to a high level.

Furthermore, due to the rise of the output signal of the inverter σa, the output signal of the AND gate 04) rises, and the multivibrator (19) is triggered again, and the multivibrator αH
- A high-level switching control signal is supplied to the FET (7), and the FET (7) is turned on again.

Based on the repetition of the above-mentioned operation, during the on-control period Ton in which the control signal is held at a high level, the FE
Each time T (7) is turned off and the voltage Vds decreases from the peak value to Vc, the multivibrator αθ is turned on, the FET (7) is turned on, and the FET (7) is driven at high frequency.

Therefore, when the voltage Vcls reaches its peak value due to being turned off, the FET (7) is not turned on, and after the voltage Vds drops to Vc, which is about 1/2 to 1/8 of the peak value, the FET (7) is turned off.
(7) turns on, and at this time, the drain-source capacitance Cds of FET (7) is proportional to the square of the voltage Vds.
The &lf energy of FET (7) is reduced to 1/4 to 1/9 of its peak value, and the heat generation of FET (7) is suppressed.

Note that the heat loss frequency of the FET (7) due to switching drive is eliminated.

In addition, the secondary winding (5b) based on the drive of the FET (7)
The output pulse of the diode (8
), (9) to the FET (1), and at this time, due to the smoothing of the capacitance Cgs between the gate and source of the FET (1), the gate voltage of the FET (1) becomes as shown in the second system. , is held at a nearly constant on-voltage.

Furthermore, when switching to the OFF control period in which the control signal changes to low level, the transistor 0Q forming the switching semiconductor for the discharge path is turned on, so that the charge accumulated in the capacitor Cgs is discharged, and the FET (1) is quickly turned off. do.

By the way, in the above embodiment, the control switching semiconductor [
Although this FET is used, a bipolar transistor may be used as the control switching semiconductor, and in this case, the same effects as in the embodiment can be obtained.

Further, it goes without saying that the insulated gate type power semiconductor may be an IGB or the like.

〔Effect of the invention〕

Since the present invention is configured as described above, it produces the effects described below.

High-frequency fluctuations in the voltage at the connection point between the primary winding of the pulse transformer and the control switching semiconductor based on the switching of the control switching semiconductor are extracted using a high-pass filter,
Based on the output signal of the high-pass filter, during the ON control period, each time the voltage at the connection point decreases from the peak value of the switching semiconductor under control to the drop detection threshold, the AND gate is output from the inverter. A trigger signal is supplied to the monostable multivibrator through the 6&
By supplying a switching control signal with a small pulse width, the control switching semiconductor is turned on after the voltage drops to a voltage lower than the peak value, and heat loss of the control switching semiconductor is reduced to prevent thermal runaway. be prevented,
Reliability can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a wiring diagram of one embodiment of the insulated gate power semiconductor drive circuit of the present invention, FIGS. 2(a) to (e) are timing charts for explaining the operation of FIG. 1, and FIG. A wiring diagram of a conventional insulated gate power semiconductor drive circuit, Fig. 4 (a)
) to (d) and FIGS. 5(a) and (L)) are timing charts of the operation explanation 11 in FIG. 3. (5)-Pulse transformer, (5a), (5b) ・-1
Next, secondary winding, 02...high-pass filter, so...inverter, (14)...and gate, (Section 1...r stable multivibrator.

Claims (1)

[Scope of Claims] [1] Based on a control signal that controls on and off an insulated gate power semiconductor, the power semiconductor is connected in series to the primary winding of an insulating pulse transformer during the ON control period of the power semiconductor. The control switching semiconductor is driven at high frequency, the output pulse of the secondary winding of the pulse transformer is applied to the gate of the power semiconductor, and the power semiconductor is charged by integrating the capacitance between the terminals of the power semiconductor. When switching to off control in which the output pulse is kept on and the output pulse is cut off,
A drive circuit for an insulated gate power semiconductor, which discharges accumulated charge in a capacitance between terminals of the power semiconductor by using a discharge path switching semiconductor that is turned on when the output pulse is cut off, and turns off the power semiconductor. an AND gate that is turned ON only during the ON control period by input of the control signal; and a switching control signal with a minute pulse width for high frequency driving that is triggered by a rising edge of the output signal of the AND gate and is applied to the switching semiconductor. a monostable multivibrator to supply; a high-pass filter that extracts high-frequency fluctuations in voltage at a connection point between the primary winding and the switching semiconductor based on switching of the switching semiconductor; and an inverter that binarizes and inverts the voltage at a drop detection threshold and outputs a trigger signal that rises when the voltage at the connection point drops to the threshold to the AND gate. Insulated gate power semiconductor drive circuit.