JPH026232B2 - - Google Patents
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- Publication number
- JPH026232B2 JPH026232B2 JP56192848A JP19284881A JPH026232B2 JP H026232 B2 JPH026232 B2 JP H026232B2 JP 56192848 A JP56192848 A JP 56192848A JP 19284881 A JP19284881 A JP 19284881A JP H026232 B2 JPH026232 B2 JP H026232B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- channel region
- optical trigger
- semiconductor substrate
- trigger signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
- H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
- H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
- H10F30/26—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having three or more potential barriers, e.g. photothyristors
- H10F30/263—Photothyristors
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- Light Receiving Elements (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
本発明はpnpnの4層からなる光トリガ・スイ
ツチング素子の光点弧感度の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in the optical firing sensitivity of an optical trigger switching element consisting of four pnpn layers.
光トリガ信号でスイツチングする素子は、第1
図に示すようにpE,nB,pB,nEの連続した4層領
域を具える半導体基体1と、一方の主表面11に
おいてnE層及びpBの露出面に接触したカソード電
極2と、他方の主表面12においてpE層の露出面
に接触したアノード電極3と、一方の主表面11
のnE層のカソード電極2が形成されていない面に
光トリガ信号を照射する手段4とから成つてい
る。 The element that is switched by the optical trigger signal is the first
As shown in the figure, a semiconductor substrate 1 includes a continuous four-layer region of p E , n B , p B , and n E , and a cathode electrode in contact with the exposed surface of the n E layer and p B on one main surface 11. 2, an anode electrode 3 in contact with the exposed surface of the pE layer on the other main surface 12, and one main surface 11
and means 4 for irradiating an optical trigger signal onto the surface of the nE layer on which the cathode electrode 2 is not formed.
第1図の構成ではpB層の厚みがnE層の下側で一
様となつている。このpB層の厚みはスイツチング
素子の順方向阻止電圧の大きさに略比例して決ま
る。一方点弧に必要な光トリガ信号の大きさはpB
層の厚みに比例して決まる。したがつて、第1図
の構成では、耐圧が高くなると、それと比例して
光トリガ信号が大きくなるという欠点がある。 In the configuration shown in Figure 1, the thickness of the p B layer is uniform below the n E layer. The thickness of this p B layer is determined approximately in proportion to the magnitude of the forward blocking voltage of the switching element. On the other hand, the magnitude of the optical trigger signal required for ignition is p B
It is determined in proportion to the thickness of the layer. Therefore, the configuration shown in FIG. 1 has the disadvantage that as the withstand voltage increases, the optical trigger signal increases in proportion.
本発明の目的は、上記の欠点を除去し、耐圧の
影響を受けず常に略一定大きさの光トリガ信号で
かつ高点孤感度でスイツチングし得る改良され光
トリガ・スイツチング素子を提供することにあ
る。 SUMMARY OF THE INVENTION An object of the present invention is to provide an improved optical trigger/switching element which eliminates the above-mentioned drawbacks and is capable of switching with a substantially constant optical trigger signal and high firing sensitivity without being affected by withstand voltage. be.
かかる目的を奏する本発明光トリガ・スイツチ
ング素子の特徴とするところは、隣接する層が異
なる導電型を有するように形成されたpnpnの連
続した4層を備える半導体基体と、半導体基体表
面においてそれぞれ少なくとも外側層に低抵抗接
触した一対の電極と、一対の電極間をスイツチン
グさせるための光トリガ信号を半導体基体表面に
照射する手段とを有するものにおいて、一方の中
間層と一方の外側層が電極で短絡されており、一
方の中間層内に他方の中間層と同じ導電型を有
し、一端が他方の中間層に連なり他端が一方の中
間層を通り一方の外側層に伸びるチヤンネル領域
を有し、チヤンネル領域の幅を、一方の中間層と
他方の中間層との間のpn接合を主電源電圧で逆
バイアスしたときに形成される空乏層でピンチオ
フするような寸法とし、一方の外側層表面のチヤ
ンネル領域に対応する個所に光トリガ信号を照射
する点にある。 The optical trigger switching device of the present invention that achieves the above object is characterized by a semiconductor substrate comprising four consecutive pnpn layers in which adjacent layers have different conductivity types, and at least one layer on the surface of the semiconductor substrate. A device comprising a pair of electrodes in low-resistance contact with an outer layer and a means for irradiating the surface of the semiconductor substrate with an optical trigger signal for switching between the pair of electrodes, in which one intermediate layer and one outer layer are electrodes. are short-circuited and have a channel region in one intermediate layer having the same conductivity type as the other intermediate layer, one end of which is connected to the other intermediate layer, and the other end of which extends through one intermediate layer to one outer layer. The width of the channel region is set so that it pinches off at the depletion layer formed when the pn junction between one intermediate layer and the other intermediate layer is reverse biased with the main power supply voltage, and one outer layer The point is to irradiate an optical trigger signal to a location on the surface corresponding to a channel region.
以下、本発明を実施例として示した図面に基づ
いて説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on drawings showing examples thereof.
第2図及び第3図において、1は互いに反対側
に位置する一対の主表面11,12間にnE,pB,
nB,pEの連続した4層を有する半導体基体、2は
一方の主表面11においてnE層露出面の中央部を
除く個所及びpB層の露出面に低抵抗接触したカソ
ード電極、3は他方の主表面12においてpE層の
露出面に低抵抗接触したアソード電極、4は光ト
リガ信号を照射する手段である。5は一方の主表
面11の光トリガ信号の照射個所に対応する個所
において、nBの一部をpB層を貫通してnE層に達す
るまで突出させたチヤネル領域である。このチヤ
ネル領域5は第4図に示すように、アノード電
極・カソード電極間の定格の順方向印加電圧でnB
層とpB層間に形成されているpn接合が逆バイア
スされる時に、全領域が空乏層化されてピンチオ
フ状態になるような幅Wに形成されている。空乏
層は6で示す。このように形成すれば、nE層とnB
層が接しても空乏層により電気的に隔離されるの
で、負荷電流iLが流れる心配はない。次にスイツ
チング動作を説明する。手段4により、光トリガ
信号をnE層の露出表面に照射すると光はnE層を通
りチヤネル領域5に入射する。この結果光の量子
数に比例した電子―正孔対がチヤネル領域5に発
生し、チヤネル領域を含むpE,nB,nEダイオード
領域が低インピーダンス状態となつて、ダイオー
ド領域が流れるようになる。さらに引続いて、こ
のダイオード電流により、チヤネル領域5周辺部
pE,nB,pB,nE4層領域がターンオンし、負荷電
流の流れる導通領域が広くなる。第2図及び第3
図に示す構造の素子では、nB層に形成されている
空乏層がチヤネル領域5ではnE層に接しているた
め、光入射面からこの空乏層までの距離をnE層の
厚みまで、すなわち最小約2〜3μm程度まで小
さくできる。したがつて、光源からの減衰を少な
くして、チヤネル領域5に入射できるので、素子
を導通状態にするに必要な光エネルギを少なくで
きる特徴がある。またチヤネル領域5を含むpE,
nB,nEダイオード領域を4層構造であるpE,nB,
pB,nE領域の場合に比較して約1/2以上速くタ
ーンオンできる特徴がある。何故ならば、nB層が
高電界であるチヤネル領域5によりnE層に接触し
ているので、光により空乏層内に発生した電子、
正孔のpE層及びnE層方向への走行時間が、pE,
nB,pB,nEサイリスタの場合に比較してpB層内で
の走行時間だけ速くなるからである。 In FIGS. 2 and 3, 1 indicates n E , p B ,
A semiconductor substrate having four consecutive layers of n B and p E ; 2 is a cathode electrode in low resistance contact with the exposed surface of the p B layer and the exposed surface of the p B layer on one main surface 11; 2; 4 is an anode electrode in low resistance contact with the exposed surface of the pE layer on the other main surface 12, and 4 is a means for irradiating a light trigger signal. Reference numeral 5 denotes a channel region in which a part of nB penetrates the pB layer and protrudes until it reaches the nE layer at a location on one main surface 11 corresponding to the irradiation location of the optical trigger signal. As shown in FIG. 4, this channel region 5 is n B
The width W is such that when the pn junction formed between the pn layer and the pb layer is reverse biased, the entire region becomes a depletion layer and becomes a pinch-off state. The depletion layer is indicated by 6. If formed in this way, n E layer and n B
Even if the layers are in contact, they are electrically isolated by the depletion layer, so there is no worry that load current i L will flow. Next, the switching operation will be explained. By means of the means 4, when an optical trigger signal is applied to the exposed surface of the nE layer, the light passes through the nE layer and enters the channel region 5. As a result, electron-hole pairs proportional to the number of light quanta are generated in the channel region 5, and the p E , n B , n E diode regions including the channel region enter a low impedance state, causing the diode region to flow. Become. Furthermore, this diode current causes the peripheral area of the channel region 5 to
The p E , n B , p B , n E four-layer regions are turned on, and the conduction region through which the load current flows becomes wider. Figures 2 and 3
In the element with the structure shown in the figure, since the depletion layer formed in the nB layer is in contact with the nE layer in the channel region 5, the distance from the light incidence surface to this depletion layer is equal to the thickness of the nE layer. That is, it can be made as small as about 2 to 3 μm. Therefore, since the light can enter the channel region 5 with less attenuation from the light source, the light energy required to bring the element into a conductive state can be reduced. Also, p E including channel region 5,
n B , n E The diode region has a four-layer structure p E , n B ,
It has the characteristic that it can be turned on about 1/2 or more faster than in the p B and n E regions. This is because the nB layer is in contact with the nE layer through the channel region 5 with a high electric field, so the electrons generated in the depletion layer by light,
The travel time of a hole toward the p E layer and n E layer is p E ,
This is because the travel time within the p B layer is faster than in the case of n B , p B , and n E thyristors.
上述した効果は、厚いpB層を必要とする従来の
高耐圧素子の場合に比較して、著しく大きくな
る。 The above-mentioned effects are significantly greater than in the case of conventional high-voltage devices that require a thick p B layer.
第5図は、nB層の不純物濃度が1×1014cm-3、
厚みが5μm、チヤネル領域5の幅が2μmでチヤ
ネル領域5の長さが75μmと10μmの場合、アノ
ード電極・カソード電極間に65Vの電圧を印加し
た状態でのチヤネル領域5の中心部を通る電位分
布を、半導体の基本方程式(ポアソン方程式、キ
ヤリヤの流れの連続式)を数値計算して解き、求
めた結果である。チヤネル領域5内に負の電位す
なわちnE層からnB層へ流れる電子に対する障壁が
形成されており、阻止状態になつている。この障
壁はチヤネル領域の幅を狭くすることにより、ま
たチヤネル領域を長くすることにより、高くな
る。 Figure 5 shows that the impurity concentration of the n B layer is 1×10 14 cm -3 ,
When the thickness is 5 μm, the width of the channel region 5 is 2 μm, and the lengths of the channel region 5 are 75 μm and 10 μm, the potential passing through the center of the channel region 5 when a voltage of 65 V is applied between the anode electrode and the cathode electrode The distribution was obtained by numerically calculating and solving the basic semiconductor equations (Poisson's equation, carrier flow continuity equation). A negative potential, ie, a barrier against electrons flowing from the nE layer to the nB layer, is formed in the channel region 5, and the channel region 5 is in a blocking state. This barrier can be increased by narrowing the width of the channel region and by increasing the length of the channel region.
第6図は、第5図の場合に対応する順方向阻止
特性である。チヤネル領域の長さが10μmの場
合、アノード電極・カソード電極間印加電圧VAK
=150Vでのリーク電流は1.2×10-7A/cm2であり
非常に小さい。チヤネル領域の長さが7.5μmでは
3×10-5A/cm2であり小さい。このように第2図
及び第3図の構造により目標の耐圧が得られかつ
光点弧感度の高い高速光トリガスイツチング素子
を実現できる。 FIG. 6 shows forward blocking characteristics corresponding to the case of FIG. When the length of the channel region is 10 μm, the voltage applied between the anode electrode and the cathode electrode V AK
The leakage current at =150V is 1.2×10 -7 A/cm 2 , which is very small. When the length of the channel region is 7.5 μm, it is 3×10 −5 A/cm 2 , which is small. As described above, with the structures shown in FIGS. 2 and 3, it is possible to realize a high-speed optical trigger switching element that can obtain the target breakdown voltage and has high optical ignition sensitivity.
第7図は、本発明の他の実施例である。第7図
aの実施例では、第2図及び第3図に示す実施例
において、チヤネル領域5とnE層との間にpB層よ
りも薄いp型半導体層7を形成したことを特徴と
している。このp層7を設けることにより、チヤ
ネル領域5の幅を広くしても、またpB層の厚みを
薄くしても、目標の耐圧が得られる。したがつ
て、この実施例は、チヤネル領域の幅を広くし
て、有効な光入射面積を広くする場合、或いはpB
を薄くする場合に適している。 FIG. 7 shows another embodiment of the invention. The embodiment shown in FIG. 7a is characterized in that in the embodiments shown in FIGS. 2 and 3, a p-type semiconductor layer 7, which is thinner than the p B layer, is formed between the channel region 5 and the nE layer. It is said that By providing this p layer 7, the target breakdown voltage can be obtained even if the width of the channel region 5 is increased or the thickness of the p B layer is decreased. Therefore, this embodiment is useful when the width of the channel region is widened to increase the effective light incident area, or when p B
Suitable for thinning.
第7図bの実施例は、第7図aに示す薄いp型
半導体層7を形を変えて、同等の効果が得られる
ようにしたものである。この構造は例えばpB層を
拡散で形成する場合、p型不純物を拡散する時の
半導体基体1の一方の主表面面11の露出部間隙
を狭くして両側からの横方向拡散が光トリガ信号
の照射される表面下で重なり合うようにして、薄
く、かつ不純物濃度の低いp型半導体層に相当す
るp層7aを形成して実現される。即ち、p層7
aはpB層を作る時に同時に形成できるのである。 In the embodiment shown in FIG. 7b, the shape of the thin p-type semiconductor layer 7 shown in FIG. 7a is changed so that the same effect can be obtained. For example, when forming the p B layer by diffusion, this structure narrows the gap between the exposed parts of one main surface 11 of the semiconductor substrate 1 when diffusing the p-type impurity, and the lateral diffusion from both sides causes the optical trigger signal to be transmitted. This is realized by forming a thin p-layer 7a corresponding to a p-type semiconductor layer with a low impurity concentration so as to overlap each other under the irradiated surface. That is, p layer 7
A can be formed at the same time as the p and B layers.
第8図は、第7図aの実施例において、pB層の
厚みを5μm、表面不純物濃度を1×1018cm-3、nB
層の厚みを5μm、不純物濃度を1×1014cm-3、p
層7の厚みを2μm、表面不純物濃度を5×1015cm
−3とした場合の順方向阻止特性の一例である。チ
ヤネル領域5の長さを5μmと短かくしても、チ
ヤネル領域5の幅が2μmでは150Vを阻止できる。
またチヤネル領域5の幅を11μmと広くしても
100Vを阻止できる。この場合p層7の厚みが2μ
mと薄いので光源4からの光は途中で減衰するこ
となくチヤネル領域5に入射する。またp層が
2μmと薄いので、pE,nB,pB,nEの4層領域を点
弧するに必要な光の強度を小さくできる。この効
果は、pB層を厚くする必要のある高耐圧スイツチ
ング素子の場合に、非常に大きい。例えば、pB層
のライフタイムが0.5μsの場合、pB層の厚みが
100μmから30μmに薄くなると、最小点弧光入力
は1/6に減少す。このように本発明では、薄い
p層7をチヤネル領域5上に設け、チヤネル領域
5をアノード電極・カソード電極間電圧でピンチ
オフ状態とすることにより、光点弧感度の大きい
高耐圧スイツチング素子を実現できる。 FIG. 8 shows the example of FIG. 7a, with the thickness of the p B layer being 5 μm, the surface impurity concentration being 1×10 18 cm -3 , and the n B
The layer thickness is 5 μm, the impurity concentration is 1×10 14 cm -3 , p
The thickness of layer 7 is 2 μm, and the surface impurity concentration is 5×10 15 cm.
This is an example of forward blocking characteristics when the value is −3 . Even if the length of the channel region 5 is shortened to 5 μm, 150V can be blocked if the width of the channel region 5 is 2 μm.
Also, even if the width of channel region 5 is widened to 11 μm,
Can block 100V. In this case, the thickness of p layer 7 is 2μ
Since the light source 4 is as thin as m, the light from the light source 4 enters the channel region 5 without being attenuated on the way. Also, the p layer
Since it is as thin as 2 μm, the intensity of light required to ignite the four layer regions p E , n B , p B , and n E can be reduced. This effect is extremely large in the case of high voltage switching devices that require a thick pB layer. For example, if the lifetime of the p B layer is 0.5 μs, the thickness of the p B layer is
As the thickness decreases from 100 μm to 30 μm, the minimum ignition light input decreases by a factor of 6. In this way, in the present invention, by providing the thin p layer 7 on the channel region 5 and putting the channel region 5 in a pinch-off state with the voltage between the anode electrode and the cathode electrode, a high breakdown voltage switching element with high light ignition sensitivity is realized. can.
第9図及び第10図は、第2図及び第3図に示
すスイツチング素子を同一の半導体基板内に多数
並列配置した場合の一例である。チヤネル領域5
を広くして、光点弧によるターンオン領域が広く
なるようにしてある。この目的のためには、カソ
ード電極側から見たチヤネル領域5のパターンは
円状、放射状、或はその他任意の形状にできる。 FIGS. 9 and 10 show an example in which a large number of switching elements shown in FIGS. 2 and 3 are arranged in parallel within the same semiconductor substrate. Channel area 5
is widened to widen the turn-on area by light ignition. For this purpose, the pattern of the channel region 5 viewed from the cathode electrode side can be circular, radial, or any other arbitrary shape.
第11図及び第12図は本発明の他の実施例で
ある。第9図及び第10図の実施例と比べて、カ
ソード電極2の構造が異なるのみである。この実
施例では、nE層の中央部の全表面にカソード電極
2が接続されていない。光がチヤネル領域5を囲
んでいるpE,nB,pB,nE4層領域にも入射するの
で、この4層領域が速くターンオンする。したが
つて、立ち上がりの速い電流をスイツチング素子
に流すことができる。 FIGS. 11 and 12 show other embodiments of the present invention. Compared to the embodiments shown in FIGS. 9 and 10, only the structure of the cathode electrode 2 is different. In this embodiment, the cathode electrode 2 is not connected to the entire surface of the central part of the nE layer. Since the light also enters the four-layer region p E , n B , p B , n E surrounding the channel region 5, these four-layer region turns on quickly. Therefore, a rapidly rising current can be passed through the switching element.
第13図は、本発明の他の実施例である。第2
図及び第3図に示す実施例を増幅形ゲート方式を
採用したスイツチング素子の補助スイツチング素
子部分ThAに応用した一例である。ThMは主スイ
ツチング素子である。光点弧感度の大きい、しか
もターンオン時の順電流上昇率耐量の大きい光ト
リガ・スイツチング装置を実現できる。 FIG. 13 shows another embodiment of the invention. Second
This is an example in which the embodiment shown in the figures and FIG. 3 is applied to an auxiliary switching element portion Th A of a switching element employing an amplified gate method. Th M is the main switching element. It is possible to realize an optical trigger switching device with high optical ignition sensitivity and high forward current increase rate tolerance during turn-on.
第14図は、第7図に示す実施例を、増幅形ゲ
ート方式を採用したスイツチング素子の補助スイ
ツチング素子部分ThAとして使用した場合であ
る。第13図の場合と同様な効果が得られる。さ
らに、第9図及び第10図並びに第11図及び第
12図の実施例を増幅形ゲート方式を採用した素
子の補助素子部分として利用することにより、タ
ーンオン時の順電流上昇率耐量の大きい光トリ
ガ・スイツチング装置を実現できる。 FIG. 14 shows a case where the embodiment shown in FIG. 7 is used as an auxiliary switching element portion Th A of a switching element employing an amplification type gate method. The same effect as in the case of FIG. 13 can be obtained. Furthermore, by using the embodiments shown in FIGS. 9 and 10, as well as FIGS. 11 and 12 as an auxiliary element part of an element that employs an amplification type gate method, it is possible to make a light beam with a large forward current increase rate at turn-on. A trigger switching device can be realized.
なお、光源4の代りに、γ線、α線等の電子―
正孔対発生源を用いた場合も同様な効果が得られ
ることは云うまでもない。 Note that instead of the light source 4, electrons such as γ rays and α rays can be used.
It goes without saying that similar effects can be obtained when a hole pair generation source is used.
第1図は従来の光トリガ・スイツチング素子の
概略断面図、第2図は本発明光トリガ・スイツチ
ング素子の一実施例を示す概略平面図、第3図は
第2図の―線に沿う断面図、第4図は第3図
の素子の阻止状態での断面図、第5図は第4図の
チヤネル領域の中心部を通る電位分布図、第6図
は第2図及び第3図の素子の順方向阻止特性図、
第7図a,bはそれぞれ本発明の他の実施例を示
す断面図、第8図は第7図aの素子の順方向阻止
特性図、第9図は本発明の別な実施例を示す平面
図、第10図は第9図の―線に沿う断面図、
第11図は本発明の更に他の実施例を示す平面
図、第12図は第11図のXII―XII線に沿う断面
図、第13図は本発明の更に別の実施例を示す断
面図、第14図は本発明の異なる実施例を示す断
面図である。
1…半導体基体、2…カソード電極、3…アノ
ード電極、4…光トリガ信号の照射手段、5…チ
ヤネル領域。
FIG. 1 is a schematic cross-sectional view of a conventional optical trigger switching device, FIG. 2 is a schematic plan view showing an embodiment of the optical trigger switching device of the present invention, and FIG. 3 is a cross-sectional view taken along the line - in FIG. 4 is a cross-sectional view of the device in FIG. 3 in a blocked state, FIG. 5 is a potential distribution diagram passing through the center of the channel region in FIG. 4, and FIG. Forward blocking characteristic diagram of the element,
FIGS. 7a and 7b are cross-sectional views showing other embodiments of the present invention, FIG. 8 is a forward blocking characteristic diagram of the element in FIG. 7a, and FIG. 9 is a diagram showing another embodiment of the present invention. A plan view, FIG. 10 is a sectional view taken along the line - in FIG. 9,
FIG. 11 is a plan view showing still another embodiment of the present invention, FIG. 12 is a sectional view taken along line XII-XII in FIG. 11, and FIG. 13 is a sectional view showing still another embodiment of the present invention. , and FIG. 14 are cross-sectional views showing different embodiments of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor base, 2... Cathode electrode, 3... Anode electrode, 4... Light trigger signal irradiation means, 5... Channel region.
Claims (1)
を有するように形成されたpnpnの連続した4層
を備え、一方の主表面に外側のn層と隣接する中
間のp層とが露出し、他方の主表面に外側のp層
が露出する半導体基体と、半導体基体の両主表面
においてそれぞれ少なくとも各外側層に低抵抗接
触した一対の電極と、一対の電極間をスイツチン
グさせるための光トリガ信号を半導体基体の一方
の主表面に照射する手段とを有するものにおい
て、 一方の電極は外側のn層の中央部を除く周縁部
及び中間のp層に低抵抗接触しており、 外側のn層の一方の電極に接触していない個所
の直下のみに位置し、外側のn層より低不純物濃
度を有し、中間のp層を貫通して一端が外側のn
層に他端が中間のn層にそれぞれ連なるn型のチ
ヤンネル領域を有し、 チヤンネル領域の幅を、一対の電極間に定格電
圧を印加して中間のp層と中間のn層との間の
pn接合を逆バイアスしたときに形成される空乏
層でピンチオフするような寸法とし、 外側のn層のチヤンネル領域に対応する個所の
露出表面に光トリガ信号を照射することを特徴と
する光トリガ・スイツチング素子。[Claims] 1. Four consecutive pnpn layers are formed between a pair of main surfaces so that the adjacent layers have different conductivity types, and one main surface has an outer n layer and an adjacent intermediate layer. a semiconductor substrate in which a p-layer is exposed and an outer p-layer is exposed on the other main surface; a pair of electrodes each in low resistance contact with at least each outer layer on both main surfaces of the semiconductor substrate; and means for irradiating an optical trigger signal for switching onto one main surface of the semiconductor substrate, wherein one electrode is in low resistance contact with the periphery of the outer n-layer excluding the center and the intermediate p-layer. It is located just below the part of the outer n-layer that is not in contact with one of the electrodes, has a lower impurity concentration than the outer n-layer, and penetrates the middle p-layer so that one end is connected to the outer n-layer.
Each layer has an n-type channel region whose other end is connected to the intermediate n-layer, and the width of the channel region is set between the intermediate p-layer and the intermediate n-layer by applying a rated voltage between a pair of electrodes. of
The optical trigger is characterized in that the dimensions are such that the p-n junction is pinched off at the depletion layer formed when the p-n junction is reverse biased, and the optical trigger signal is irradiated onto the exposed surface of the outer n-layer corresponding to the channel region. switching element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56192848A JPS5895866A (en) | 1981-12-02 | 1981-12-02 | Optical trigger switching element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56192848A JPS5895866A (en) | 1981-12-02 | 1981-12-02 | Optical trigger switching element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5895866A JPS5895866A (en) | 1983-06-07 |
| JPH026232B2 true JPH026232B2 (en) | 1990-02-08 |
Family
ID=16297974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56192848A Granted JPS5895866A (en) | 1981-12-02 | 1981-12-02 | Optical trigger switching element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5895866A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3338234B2 (en) * | 1995-05-17 | 2002-10-28 | 三菱電機株式会社 | Light trigger thyristor and manufacturing method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5320885A (en) * | 1976-08-11 | 1978-02-25 | Semiconductor Res Found | Electrostatic induction type semiconductor device |
| JPS5924546B2 (en) * | 1977-06-10 | 1984-06-09 | 株式会社日立製作所 | Field effect semiconductor switching device |
| JPS5460881A (en) * | 1977-10-24 | 1979-05-16 | Mitsubishi Electric Corp | Optical action type semiconductor device |
| JPS54106176A (en) * | 1978-02-08 | 1979-08-20 | Hitachi Ltd | Field effect switching element |
| JPS6013310B2 (en) * | 1979-03-15 | 1985-04-06 | 三菱電機株式会社 | semiconductor equipment |
| JPS55128870A (en) * | 1979-03-26 | 1980-10-06 | Semiconductor Res Found | Electrostatic induction thyristor and semiconductor device |
-
1981
- 1981-12-02 JP JP56192848A patent/JPS5895866A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5895866A (en) | 1983-06-07 |
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