JPH0262597A - display control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a document preparation system such as a word processor or an electronic typewriter.

Conventional technology Display devices such as European language word processors and electronic typewriters use a character display control method based on characters, which allows for underlining, inverted display, gap display, and bold (thick characters) for displayed characters. Display character attributes such as (
The configuration is such that it can be displayed by adding attributes (hereinafter referred to as attributes). FIG. 5 is a block diagram showing a conventional character display control system. In general, character display control systems use a rectangular area called a character box as a unit of display control, as shown in FIG. The character box in Figure 6 is arranged in a grid pattern with the minimum pixels (hereinafter referred to as dots) on the screen being 8 vertically and 16 horizontally.
It is composed of individuals. In Figure 5, 1 is a CRT.
It is a CRT control unit that controls 9 and processes? A horizontal synchronizing signal and a vertical synchronizing signal necessary for the CRT 9 and a display address for accessing the display memory 2 are generated by the a-check signal from the 1E13. 2 is a display memory and a processing unit 13
The character codes and attribute codes of characters to be displayed by the CRT 9 are stored under the control of the CRT 9. Reference numeral 3 denotes an attribute latch circuit which holds the attribute code read out from the display memory 2 at the timing of the latch clock LC. 4 is the character code latch circuit and display memory 2
The character code read from is held at the timing of the latch clock LC. A font memory 6 stores a character pattern corresponding to a character code, and outputs a character pattern composed of parallel information using the character code held in the character code latch circuit 4 as an address. In general, data in font memory is such that the horizontal arrangement of character patterns as shown in Figure 3 corresponds to the presence or absence of that pattern.
or arranged as the value of l. One character code consists of a total of 16 bytes, with 1 byte consisting of 8 horizontal bits. Therefore, by inputting the value of this character code to the upper address of the font memory and the rask address indicating the vertical position in the character pattern to 4 bits, the character font pattern of 1 byte in the horizontal direction of the corresponding character code can be input. is output as data. 8 is a parallel serial converter and font memory 6
The character pattern composed of parallel information from the CRT 9 is converted into a serial pattern to be displayed on the CRT 9 in synchronization with the dot clock DCL. 28 is an AT code decoder which decodes the attribute code according to the attribute code held in the attribute latch circuit 3. 27 is a serial pattern converter which converts the serial pattern from the parallel serial converter 8 into 8 according to the signal from the attribute code decoder circuit 28.
Converts bit serial data into patterns such as inversion, O fixed, 1 fixed, etc. Reference numeral 9 denotes a CRT cathode ray tube display, which visually outputs the serial pattern from the serial pattern converter 27 in synchronization with the horizontal synchronization signal and vertical synchronization signal from the CRT control section 1.

FIG. 7 shows the timing from the CRT control section 1 to the attribute latch circuit 3 and character code latch circuit 4. DCL is a signal with the highest frequency that defines the dot period of the video signal, and is formed by the processing section 13 and applied to the parallel-serial converter 8 and the serial pattern converter 27. CCL is dot clock DCL 8
This is a control signal obtained by dividing the frequency by a factor of 1, and is applied to the CRT control section l. CRTilJi (Ii9ffl uses this control signal CCL to generate the timing of the address signal, horizontal synchronization signal, and vertical synchronization signal of the display memory 2.The arrows in the timing chart correspond to the signal flows in the block diagram. MA indicates the generation timing of the address of the display memory 2 generated by the CRT control unit 1. DB indicates the output timing of data from the display memory 2. L and C are generated by the processing unit 13 at latch timing. , the attribute latch circuit 3 and the character code latch circuit 4 hold the data from the display memory 2 in synchronization with the rise of this signal. CP is the output timing of the character data pattern output from the font memory 6. , which is 8-bit parallel.AT,C
C indicates the output timing with the character code and attribute code output from the display memory 2. SP is connected to the dot clock 23 by the parallel serial converter 8.
This shows the output timing of serial data that is converted in synchronization with . AT” is attribute code decoder circuit 2
8 shows the output timing of attribute data output from 8. Video is serial pattern converter 2
7 shows the output timing. Here, the data of the attribute code must be held during the timing period when the corresponding serial data exists, but as shown in FIG. 7, the timing position with respect to the serial data is shifted. Therefore, after the attribute code is decoded, it must be latched in synchronization with the serial data.

Problems to be Solved by the Invention However, in the conventional configuration, as shown in FIG. 4, data conversion is performed after pattern data CP output from the font memory is converted to -H serial data, so it is difficult to compare with parallel data. The data width is short (it is difficult to synchronize the timing with the attribute data. Especially in custom LSI such as gate arrays, this synchronization circuit requires a large number of circuit elements, which increases the cost. Furthermore, it has been difficult to plan for common use with liquid crystal display devices and plasma display devices.

Means for Solving the Problems The present invention provides conversion means for directly converting a character pattern composed of parallel information outputted from a character pattern storage means into a pattern in a parallel state according to an attribute code that defines its display form. Ta.

Effect: With this configuration, pattern conversion is performed on parallel data and then parallel-to-serial conversion is performed, so a synchronization circuit is not required.

EXAMPLE Hereinafter, an example of the present invention will be described in detail with reference to the drawings. First, FIG. 1 is a block diagram of a display control device in an embodiment of the present invention. 1 is a CRT control unit, 2 is a display memory, 3 is an attribute code latch circuit, 4 is a character code latch circuit, and 5 is an attribute for converting the attribute code into 2-bit control codes PATO and PATI according to the present invention. 6 is a font memory, 7 is a parallel attribute converter according to the present invention, 8 is a parallel to serial converter, and 9 is a CRT. A latch clock LCL, which is a latch timing signal, is connected to the attribute latch circuit 3 and the character code latch circuit 4. A memory address 11 accessed by the processing section 13, a display data address MA25 output from the CRT control section 1, and a data bus 10 are connected to the display memory 2. The data bus 1o is further connected to an attribute latch circuit 3, a character code latch circuit 4, and a data bus of a processing section 13. CR
The T control unit 1 outputs a rask address RA indicating the vertical scanning position of the character box, and this rask address RA is connected to a lower address of the font memory 6. Further, a vertical synchronizing signal and a horizontal synchronizing signal are connected to the CRT 9.

The operation of the display control device configured as described above will be described below, but the operations from the CRT control section 1 to the attribute latch circuit 3 and character code latch circuit 4 are the same as those in the conventional example, and therefore the explanation will be omitted. FIG. 2 shows a timing chart of the above blocks. Everything from the dot clock DCL to the character data pattern CP is the same as the conventional one. Attribute latch circuit 3
The attribute code output from the attribute decoder circuit 5 is converted into 2-bit control signals PATI and PATO. Generally, attribute codes are formed by blink, reverse, underline, underline, highlight, etc. Reverse is the character font that makes up the character (the circled part in Figure 6, this is called the foreground) and the part excluding the character font in the character box (this is called the background).
It has the meaning of reversing the . Underline is an attribute that draws a horizontal line under a character. For example, if the underline attribute is added to the displayed character "A", it will be displayed as "8".

Highlighting is a function that increases the brightness of the foreground of characters. Blink is a function that causes the foreground of text to blink. In addition to these character attributes, there is another pattern called a cursor that indicates the current display position. Generally, the signal indicating the cursor position is often output from the CRT control section 1. There are various factors that cause the patterns of these display character fonts to be converted, but these can be summarized into four conversion methods as shown in Table 2.

One always outputs 1 regardless of the input pattern data, one outputs the input pattern as is, one inverts the input pattern and outputs it, and one input It always outputs O regardless of the pattern. FIG. 3 shows this attribute decoder 5 in more detail. Circuits 33 and 34 are logic circuits showing exclusive OR, and 36.41
．． 45 is a logic circuit showing logical product. 42.43.4
4 is a NAND circuit showing logical product of negative output, 38.39
．． Reference numeral 40 denotes an OR circuit that performs a logical sum, 37 a NOR circuit that performs a logical sum of negative outputs, and 41 an N07 circuit that performs a negative output. CD1sp is a timing signal indicating the cursor position, RVS is a reverse attribute signal,
RvS is a reverse attribute signal, BLK is a blink attribute, BL INK INTB is an interval signal indicating the synchronization position of the blink period, DBU is a signal indicating a double underline attribute, RA3~
O is a signal indicating a raster address, UND is a signal indicating an underline attribute, and D I SPTMG is a display timing signal indicating horizontal and vertical display periods and blanking periods. The line to be displayed in UND is the raster address Fh (h indicates hexadecimal), and the DBU is Eh and Fh. Since UND and DBU are the same except for the raster address, they are logically summed and combined as UNDER46, and B
LK and BLINKINTB are logically ANDed and are valid only during the interval period. This AND output 47 is
Combined as LINK UNDER, BLINKlRVS
, the output PATl decoded from CDl5P,
The PATO logical table is as shown in Table 1. The values of decoded outputs PATI and PATO are generated according to this logic table.

In addition, when D I SPTMG is 0 indicating the retrace period of the synchronization signal, the display data must always be 0. Therefore, the output of PATL, PATO and DISPTM
This function is realized by using an OR circuit of G. PA output from attribute decoding circuit 5
TI and PATO are parallel attribute converters 7
is input.

The parallel attribute converter 7 performs pattern conversion on the character pattern data output from the font memory 6 in accordance with the PATI and O control signals. FIG. 4 shows a more detailed circuit of the bartuffs in Table 1 of this parallel attribute controller. Block 31 shows a circuit for bit 7 of the character pattern data, and the same blocks from bit 6 to bit 0 are arranged below. The circuit 32 is And-Or-1nvrto
It is an r-gate and consists of only a few circuit elements. The circuit shown in FIG. 4 realizes the conversion shown in Table 2.

Table 2 Effects of the Invention In the present invention, parallel character pattern data read from the font memory is subjected to pattern conversion corresponding to its attributes while remaining parallel, and then converted to a serial pattern. The timing circuit required when converting a pattern to a pattern corresponding to its attributes is no longer required, and C
It becomes possible to provide a display i1J control device that can be used not only for RT but also for liquid crystal displays, plasma displays, and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a display control device in an embodiment of the present invention, FIG. 2 is a timing chart of each signal in FIG. 1, and FIG. 3 is an attribute in an embodiment of the present invention. A logic circuit diagram showing an example of a code decoder,
FIG. 4 is a logic circuit diagram showing an example of a parallel attribute converter in an embodiment of the present invention, FIG. 5 is a block diagram showing the configuration of a conventional display control device, and FIG. A pattern diagram showing an example, FIG. 7, is a timing chart of signals appearing in a conventional display control device. Memory, 7... Barrel attribute converter,
8...Parallel serial converter.

Claims (1)

[Scope of Claims] A character pattern storage means that stores a character pattern, a storage means that stores an attribute code that defines a display form of the character pattern, and parallel information output from the character pattern storage means. a converting means for converting a character pattern according to an attribute code stored in the storage means; and a parallel converting means for converting a character pattern composed of parallel information converted by the converting means into a character pattern composed of serial information. A display control device comprising: serial conversion means;