JPH0263280B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a semiconductor memory device in which it is possible to determine whether the function of a decoder is good or bad without writing/reading data to/from a memory cell array. .

(2) Background of the technology Semiconductor storage devices are required to be able to A: write and/or read any data at any address, B: write and/or read any data, and C: store the written data. Currently, these functions are checked by actually writing/reading data to/from all memory cells.

(3) Prior Art and Problems A decoder for a semiconductor memory device is required to have the following two functions.

Only one selection line out of a plurality of selection lines is selected (in other words, one selection line is always selected, and multiple selection lines are not selected at the same time).

Different selection lines are selected for different address signals (in other words, the same selection line is not selected multiple times for different address signals, and no address signal causes the corresponding selection line to be selected. selected and that no selection line is not selected at all).

Conventionally, these functions have been tested by actually writing data into a memory cell and reading it out.

However, in order to test the decoder function using this method, it is necessary to create a special data pattern for the decoder function test. This is because simply writing data to a memory cell and reading it does not necessarily mean that the same selection line is selected at two or more different addresses, or that multiple selection lines are selected at the same time. This is because it cannot be determined.

Furthermore, with UV-erasable EPROM, once data is written, it takes time to erase it.
If the above method is used, the test efficiency will be reduced. Also, data can only be written once,
The structure is such that written data cannot be erased.
OPROM (One time Programmable Read Only)
With regard to memory), the method described above cannot be adopted, and there was a problem in that it was difficult to guarantee sufficient reliability of the decoder's function.

(4) Purpose of the Invention The present invention is directed to writing/writing data to memory cells.
It is an object of the present invention to realize a semiconductor memory device in which the function of a decoder can be tested without performing reading, and to solve the above-mentioned problems.

(5) Structure of the Invention The above object is to provide a memory cell array, a decoder that generates a selection signal for selecting a memory cell corresponding to an address signal from the memory cell array, and a decoder connected to a plurality of output terminals of the decoder. a decoder function determination circuit, the decoder function determination circuit including a shift register to which a plurality of outputs of the decoder are input as shift control inputs, and the shift register has a number of stages corresponding to the number of outputs of the decoder. and is configured such that data is shifted in response to the selection signal, and during testing,
By sequentially changing the addresses given to the decoder, it can be determined that the input data input to the shift register is shifted through the shift register and output when the decoder function is normal. This is achieved by a semiconductor memory device having the following characteristics.

(6) Embodiment of the invention Hereinafter, an embodiment of the present invention will be described in more detail with reference to the drawings. FIG. 1 is a block diagram of a semiconductor memory device which is an embodiment of the present invention. In the figure, 1 is a memory cell array, 2 is an X decoder, 3 is an address input buffer, 4 is a Y decoder, 5 is a sense amplifier/write amplifier, 6 is a control signal generation circuit, and 7 is a decoder function determination circuit.

In FIG. 1, memory cell selection is performed by selecting a word line with the output of the This is done via amplifier 5. Further, the control signal generating circuit 6 generates an internal circuit control signal in response to, for example, a write enable signal or a chip select signal applied from the outside. This embodiment differs from the conventional one in that a decoder function determination circuit 7 is provided.

Before explaining the decoder function determination circuit 7 according to the present invention, the configuration of the X decoder 2 shown in FIG. 1 will be briefly explained.

FIG. 2 is a diagram showing an example of the circuit configuration of the X decoder 2, where WL ₀ to WL _N are word lines, 21 to 2
N is a decoding circuit, Q ₁ to _{Q o} are enhancement type MOS transistors, and Q _D is a depletion type.
It is a MOS transistor. Furthermore, the decoding circuit 2
Since the circuit configuration of 2 to 2N is the same as that of 21, illustration thereof is omitted. In Figure 2, for example, a transistor
When the signals input to the gates of Q ₁ to _{Q o} all become low level and all Q ₁ to _{Q o} are cut off, the word line WL ₀ becomes high level and is selected. Decode circuits 22 to 2N also operate in the same manner as 21.
However, the address signals input to the gates of Q ₁ to _{Q o} are different for each decoding circuit, so that two or more word lines are not selected at the same time. Note that the basic circuit configuration of the Y decoder 4 is the same as that of the X decoder 2, except that the input address signal is different from that of the X decoder 2.

In the present invention, the circuit shown in FIG. 5 checks whether the above-mentioned functions that such a decoder should have are working properly. FIG. 6 is a timing diagram for explaining the operation of the circuit shown in FIG. 5. In the figure, TD _IN is input data, TD _put is output data, TE is an enable signal, and t ₁ and t ₂ are clock signals. The transistors marked with black dots are depletion type MOS transistors, and the others are enhancement type MOS transistors.

The circuit in Figure 5 is a type of shift register,
A portion SF surrounded by a dashed line indicates a one-stage dynamic shift register. This circuit first inputs the input data TD _IN , and inputs an address signal to sequentially select WL ₀ to WL _N , thereby sequentially transferring the input data TD _IN . If there is no problem with the decoder, after selecting WL _N , TD _IN and TD _OUT
matches. On the other hand, if a decode output does not occur when a certain address signal is input, or if a certain word line is selected multiple times, TD _IN is not transferred to the output stage of the decoder function determination circuit 7, and TD _IN and
Since TD _OUT does not match, it is clear that the decoder is defective.

The operation shown in FIG. 5 will be explained in more detail below with reference to FIG. To enter the test mode, first set the enable signal TE to logic "1" to turn on the transistor _TE . Then the clock signal t ₁ ,
t ₂ (t ₂ is internally generated based on t ₁ ), and an address signal is input to the address input buffer 3 so that WL ₀ to WL _N sequentially become logic "1".

For example, if clock t1 becomes logic "1" while WL ₀ is logic " ₁ ", T ₁₁ and T ₁₂ turn on, and the level of TD _IN goes to capacitor C ₀ via T ₁₁ and T ₁₂ . be transferred. Then, when clock _t1 returns to logic "0", _T11 is cut off and the capacitor
The potential of C ₀ , that is, the gate potential of T ₁₄ is held at the level transferred from TD _IN . If TD _IN is logic "1", the gate potential of T ₁₄ is also logic "1", so T ₁₄ is turned on and the level of node N ₀ becomes logic "0".

Next, when WL ₁ becomes logic "1" and clock t ₁ becomes logic "1", T ₂₁ and T ₂₂ turn on, and node N ₁
The level of is transferred to capacitor C via T ₂₁ and T ₂₂ . When clock _t1 returns to logic “0”,
The level of N ₁ is held on capacitor C ₁ . Thereafter, the signal is transferred to capacitor C _N in the same manner. If the decoder is functioning normally, the potential of C _N , that is, the gate potential of T _N4 , is at logic "0" when data is transferred to C _N.

Now, when data is transferred to C _N , WL _N is at logic "1" and clock _t1 is at logic "1". Further, clock t2 _, which is the inverted logic of clock _t1 , is at logic "0". At this time T _N1
(not shown), T _N2 is turned on, and the logic "0" of node N _N-1 (not shown) is transferred to C _N , that is, the gate of T _N4 , through these T _N1 and T _N2 . Therefore, T _N4 is turned off, and node N _N becomes logic "1", and since T _Z2, which uses this as a gate, is turned on, node N _Z1 becomes logic "0". Also, at this time, from the above conditions, T _Z3 and T _Z4 are on, T _Z5 and T _Z6 are off, and the logic “1” of node N _N is node N _Z2 , that is,
To the gate of T _F2 , the logic "0" of node N _Z1 is transferred to the gate of node N _Z3 or T _F6 , respectively.
Therefore, since T _F2 is turned on and T _F6 is turned off, node N _F1 becomes logic "0" and T _F5 is also turned off. Therefore, N _F2 becomes logic "1" and T _F3 turns off.
After that, when clock _t1 returns to logic "0", clock _t2 becomes logic "1" and T _Z3 and T _Z4 are turned off.
Since T _Z5 and T _Z6 are turned on and nodes N _Z2 and N _Z3 both become logic "0", the flip-flop circuit constituted by T _F1 to T _F6 has the above-mentioned logic, that is, node N _F1 is logic "0". ”, node N _F2 , TD _OUT , holds logic “1”. After this hold, TE becomes logic "1" and clock _t1 becomes logic "0".
will continue until the power is turned off. In other words, the circuits T _Z1 to T _Z6 and T _F1 to _{T F6} are added to provide the function of continuously outputting the check results of the aforementioned decoder to TD _OUT in a static manner.

If the decoder is functioning normally like this
The logic of TD _IN and TD OUT is transferred by the shift register of TD IN (N+1) stages (the output of the decoder, that is, the number of selection lines is a power of 22, so (N+1) is an even number) and the logic of TD _IN and TD _OUT is transferred at the point indicated by the arrow CH. You can check for a match.

The above operation is performed in the same way when TD _IN is set to logic "0".

On the other hand, even one of WL ₀ to WL _N is logic “1”
If this is not the case, or if the decode output appears on the same line more than once, TD _IN will not be transferred correctly.
TD _IN and TD _OUT after the transfer end do not match, indicating that the decoder is defective. In other words, it is possible to detect whether the decoder is good or bad depending on whether the decoder sequentially selects the selection lines in response to each sequentially applied address signal.

In this example, to ensure further accuracy,
Just look at the coincidence of TD _IN and TD _OUT both when TD _IN is set to "1" and when it is set to "0".
This is because the circuit shown in FIG. 5 itself may be defective. The above-described feature of the circuit shown in Figure 5 is that the same decode output occurs multiple times, and even if a certain decode output does not occur at all, for example, when WL ₃ should be selected,
The point is that it is possible to detect failures such as WL ₀ being selected and WL ₃ not being selected at all.

Next, the decoder function determining circuit shown in FIG. 5 described above can check the above-mentioned function, but cannot check the function . As mentioned above, it is desirable to check the following two points when determining the function of the decoder. Therefore, it is conceivable to provide a decoder function determination circuit 7 that checks whether the above-mentioned functions that the decoder shown in FIG. 3 should have function normally. In the figure, T _D0 to T _DN are enhancement type MOS transistors, T _L is a depletion type MOS transistor, CP ₁ and CP ₂ are comparators, and G is a NOR gate.

Note that WL ₀ to _{WL N} indicate that each output of the X decoder 2 in FIG. 2 is input. Furthermore, T _D0
~T _DN are all transistors with the same characteristics.

This decoder function determination circuit 7 includes a transistor
The function of the decoder is tested using the fact that the potential at point A is different when only one of _TDO to _TDN is turned on and when a plurality of them are turned on. The operation of the circuit shown in FIG. 3 will be explained below using FIG. 4. In FIG. 4, V _RD0 to V _RD2 indicate the potential V _RD at point A in FIG. 3, and these have the following relationship.

V _RD0 : When all T _D0 to T _DN are off V _RD1 : When only one of T _D0 to T _DN is on V _RD2 : When two of T _D0 to T _DN are on Figure 3 , the reference voltage V ₁ is set between V _RD0 and V _RD1 , the reference voltage V ₂ is set between V _RD1 and V _RD2 , and the comparator CP ₁ is selected for at least one word line. comparator _CP2 detects that two or more word lines are not selected. Therefore, if only the corresponding word line is selected in response to the address signal, the output V _SD of the NOR gate G becomes logic "1".

In other words, if only the word line corresponding to the address signal is selected when the address signal is changed sequentially, V ₁ > V _RD (= V _RD1 ) > V ₂ , and the outputs of comparators CP ₁ and CP ₂ are both logic “0”,
Since V _SD becomes logic "1" under all selection conditions, it can be seen that the decoder is functioning normally.

On the other hand, if no word line selection output is generated from the decoder for a certain address signal, V _RD
(=V _RD0 )>V ₁ >V ₂ , so the output of comparator CP ₁ becomes logic "1", the output of comparator CP ₂ becomes logic "0", and V _SD becomes logic "0". Furthermore, if two or more word line selection outputs occur simultaneously under a certain address signal condition, two or more of T _D0 to _{T DN} will be turned on, so the potential V _RD at point A will be lower than V _RD2 than V ₂ .
becomes.

At this time, the output of comparator CP ₁ is logic "0",
The output of comparator _CP2 becomes logic "1" and V _SD becomes logic "0".

By incorporating the circuit shown in Figure 3 into a semiconductor memory device, the decoder function can be easily activated by simply inputting all conditions (combinations) of address signals without writing/reading data into memory cells. You can check.

In the embodiment shown in FIG. 1, the decoder function determination circuit 7 is provided only in the X decoder 2, but it goes without saying that it may also be provided in the Y decoder 4 side. Further, the judgment output V _SD may be output to a pad on the semiconductor chip and not output to the outside of the package, or may be output from an external terminal to the outside of the package. However, when outputting V _SD to the outside of the package, it is sufficient to share the terminal used for inputting or outputting other signals.For example, if a terminal is connected to a voltage higher than the normal operating voltage, The terminal can be shared by allowing V _SD to be output to the other terminal when .

Furthermore, although the circuit in Figure 3 can be used in conjunction with the circuit in Figure 5 to perform a complete decoder function check, it is also possible to use only one of the circuits to check a range according to each function. . Furthermore, the configuration of the decoder function determination circuit 7 is not limited to the configurations shown in FIGS. 3 and 5.
It suffices if it can be checked.

(7) Effects of the invention As explained above, according to the present invention, the following effects can be obtained.

Since there is no need to create a complex test pattern and write/read it to/from actual memory cells, the time required for functional testing of the decoder is significantly reduced.

Since writing/reading of actual memory cells is not performed, a simple test device is sufficient.

Data cannot be written to the actual memory cells before the product is shipped. The functionality of decoders such as OPROM can also be tested, increasing product reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory device which is an embodiment of the present invention, FIG. 2 is a diagram showing an example of a circuit of a decoder, FIG. 3 is a diagram showing an example of another decoder function determination circuit, and FIG. Figure 4 shows the potentials V ₁ , V ₂ , and
FIG. 5 is a diagram showing the relationship between V _RD0 to V _RD2 , FIG. 5 is a diagram showing an example of a decoder function determination circuit, and FIG. 6 is a timing diagram for explaining the operation of the circuit in FIG. 5. 1...Memory cell array, 2...X decoder, 3...
Address input buffer, 4...Y decoder, 6...Control signal generation circuit, 7...Decoder function determination circuit, _CP1 , _CP2 ...Comparator, G...NOR gate,
IV...Inverter, SF...Shift register, TD _IN ...
Input data, TD _OUT ...output data.

Claims (1)

[Claims] 1. A memory cell array, a decoder that generates a selection signal for selecting a memory cell corresponding to an address signal from the memory cell array, and a decoder function connected to a plurality of output terminals of the decoder. a determination circuit, the decoder function determination circuit includes a shift register to which a plurality of outputs of the decoder are input as shift control inputs, and the shift register has a number of stages corresponding to the number of outputs of the decoder; It is configured such that data is shifted in response to the selection signal, and by sequentially changing the address given to the decoder during testing, if the decoder function is normal, the input data input to the shift register is A semiconductor memory device characterized in that the semiconductor memory device is configured such that the data is shifted through the shift register and output.