JPH0265338U - - Google Patents
Info
- Publication number
- JPH0265338U JPH0265338U JP1988144083U JP14408388U JPH0265338U JP H0265338 U JPH0265338 U JP H0265338U JP 1988144083 U JP1988144083 U JP 1988144083U JP 14408388 U JP14408388 U JP 14408388U JP H0265338 U JPH0265338 U JP H0265338U
- Authority
- JP
- Japan
- Prior art keywords
- leads
- ceramic
- ceramic container
- cavity
- seal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
- H10W72/5473—Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
第１図ａは本考案の第１の実施例の示す平面図
、第１図ｂは第１図ａのＸ―Ｘ′線断面図、第２
図は本考案の第２の実施例を示す平面図、第２図
ｂは第２図ａ図のＸ―Ｘ′線断面図、第３頭ａは
従来例を示す平面図、第３ｂは第３図ａのＸ―Ｘ
′線断面図である。 １……半導体チツプ、２……セラミツク容器、
３―１〜３―２０……リード、４……封止材（ガ
ラス）、５，５―１，５―２……ボンデイングパ
ツド、６，６―１〜６―３……ボンデイング線、
７……キヤビテイ、８……マウント材（Ａｕ―Ｓ
ｉ）、９―１，９―２……ボンデイング片、１０
……連結体。
、第１図ｂは第１図ａのＸ―Ｘ′線断面図、第２
図は本考案の第２の実施例を示す平面図、第２図
ｂは第２図ａ図のＸ―Ｘ′線断面図、第３頭ａは
従来例を示す平面図、第３ｂは第３図ａのＸ―Ｘ
′線断面図である。 １……半導体チツプ、２……セラミツク容器、
３―１〜３―２０……リード、４……封止材（ガ
ラス）、５，５―１，５―２……ボンデイングパ
ツド、６，６―１〜６―３……ボンデイング線、
７……キヤビテイ、８……マウント材（Ａｕ―Ｓ
ｉ）、９―１，９―２……ボンデイング片、１０
……連結体。
Claims (1)
- 半導体チツプを搭載するキヤビテイを備えたセ
ラミツク容器とキヤツプとで複数のリードを挾ん
で封止したサーデイツプ型半導体装置において、
前記複数のリードのうち少なくとも一つは、その
先端が延長されもしくは分岐されて前記セラミツ
ク容器に固定されていることを特徴とするサーデ
イツプ型半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988144083U JPH0265338U (ja) | 1988-11-02 | 1988-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988144083U JPH0265338U (ja) | 1988-11-02 | 1988-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0265338U true JPH0265338U (ja) | 1990-05-16 |
Family
ID=31411477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988144083U Pending JPH0265338U (ja) | 1988-11-02 | 1988-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0265338U (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04177846A (ja) * | 1990-11-13 | 1992-06-25 | Toshiba Corp | 半導体装置 |
-
1988
- 1988-11-02 JP JP1988144083U patent/JPH0265338U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04177846A (ja) * | 1990-11-13 | 1992-06-25 | Toshiba Corp | 半導体装置 |