JPH0263544U - - Google Patents
Info
- Publication number
- JPH0263544U JPH0263544U JP1988143552U JP14355288U JPH0263544U JP H0263544 U JPH0263544 U JP H0263544U JP 1988143552 U JP1988143552 U JP 1988143552U JP 14355288 U JP14355288 U JP 14355288U JP H0263544 U JPH0263544 U JP H0263544U
- Authority
- JP
- Japan
- Prior art keywords
- package
- ceramic
- glass layer
- recess
- mounting part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Die Bonding (AREA)
Description
第１図は本考案の一実施例を示す半導体装置の
断面図、第２図は従来の半導体装置を示す断面図
である。 １……セラミツク容器、２……高融点硝子層、
３……リード、４……半導体チツプ、５……ボン
デイング層、６……低融点硝子層、７……キヤツ
プ、８，９……硝子層。
断面図、第２図は従来の半導体装置を示す断面図
である。 １……セラミツク容器、２……高融点硝子層、
３……リード、４……半導体チツプ、５……ボン
デイング層、６……低融点硝子層、７……キヤツ
プ、８，９……硝子層。
Claims (1)
- セラミツク容器の凹部底面に設けた素子載置部
と、前記凹部上段水平面に設けた高隔点硝子層に
より固着して前記セラミツク容器の外部に導出さ
れたリードとを有するパツケージと、前記素子載
置部に搭載して前記リードと電気的に接続された
半導体チツプと、前記パツケージの周縁部上に重
ねたセラミツクキヤツプと、前記セラミツクキヤ
ツプと前記パツケージの間に設けて前記パツケー
ジを封止する低融点硝子層とを有することを特徴
とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988143552U JPH0263544U (ja) | 1988-11-01 | 1988-11-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988143552U JPH0263544U (ja) | 1988-11-01 | 1988-11-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0263544U true JPH0263544U (ja) | 1990-05-11 |
Family
ID=31410475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988143552U Pending JPH0263544U (ja) | 1988-11-01 | 1988-11-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0263544U (ja) |
-
1988
- 1988-11-01 JP JP1988143552U patent/JPH0263544U/ja active Pending