JPH0265569A - Video signal processing unit - Google Patents

Abstract

PURPOSE:To obtain a synchronizing signal surely synchronously with a video data by generating the synchronizing signal having a delay time larger than a delay time caused due to dispersion in components or temperature or voltage change. CONSTITUTION:A synchronizing signal S is converted into a horizontal synchronizing signal H by a horizontal synchronizing signal generating circuit 3 and into a vertical synchronizing signal V by a vertical synchronizing signal generating circuit 4. The delay times tpd1 and tpd2 in this case are delay varied with temperature or voltage. A delay clock generating counter 6 generates a frequency divider clock Q1 from a counter control signal Q and a dot clock DC. The frequency divider clock Q1 has a delay of 2 dot clocks synchronously with THE TRAIlLING OF THE synchronizing signal S. Then a flip-flop 7 receives the horizontal synchronizing signal H, the vertical synchronizing signal V and the frequency divider clock Q1 to generate a horizontal synchronizing signal H' retarded from the delay time tpd1 and a vertical synchronizing signal V' retarded than the delay time tpd2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a video signal processing device that processes a video signal, and more particularly to a video signal processing device suitable for digitally processing a composite video signal.

(Prior Art) FIG. 3 is a block diagram showing a schematic structure of a conventional video signal processing device. In this figure, 1 is an A/D converter that A/D converts a composite video signal according to a dot clock;
3 is a sync signal separation circuit that extracts the sync signal contained in the composite video signal; 3 is a horizontal f-signal generation circuit that generates a horizontal sync signal from the sync signal extracted by the sync signal separation circuit 2; 4 is a sync signal separation circuit This is a vertical synchronization signal generation circuit that generates a multiplier 11 signal from the synchronization signal extracted in step 2.

Some devices (not shown) that generate composite video signals are configured to also generate dot clocks. The A/D converter 1 receives the composite video signal and dot clock generated in this way and creates digital (video) data. Further, the horizontal synchronization signal is sent from the horizontal synchronization signal generation circuit 3 to the manual synchronization signal generation circuit 4.
A 1iI synchronization signal is obtained from . A digital video data processing unit that processes digital video data]! I! Department (
(not shown) requires digital video data of only the valid image portion, and distinguishes between the valid image portion and the ineffective image portion (blanking period) using the horizontal synchronization signal and the vertical synchronization signal.

(Problems to be Solved by the Invention) As described above, when distinguishing between digital video data using synchronization signals, digital video data and horizontal synchronization signals, ! 1. It is required that the timing with the vertical synchronization signal is always constant, but there are differences in the elements used in each part and the temperature.

If the temperature or voltage changes due to differences in voltage characteristics, the timing of the horizontal synchronization signal and t@ direct synchronization signal will change. Therefore, it is a challenge to obtain desired digital video data.

The present invention has been made in view of the above problems, and its object is to realize an ms signal processing device that can obtain a synchronization signal that is reliably synchronized with video data.

(Means for Solving the Problems) The present invention for solving the above problems includes an A/D conversion means for A/D converting an externally applied composite video signal based on an externally applied dot clock; Synchronization signal separation means for extracting a synchronization signal from a given composite video signal, synchronization signal generation means for generating a horizontal synchronization signal and a vertical synchronization signal from the synchronization signal extracted by the synchronization signal separation means, and a synchronization signal separation circuit. a counter control signal generating means for generating a counter control signal synchronized with the same 1n signal from the 1n signal; a delay clock generating means for generating a clock for delaying the horizontal open j] signal and the vertical synchronizing signal; A first flip-flop that delays a vertical synchronization signal by a delay clock, a horizontal synchronization signal delayed by the first flip-flop, and! j, i! The second flip-flop synchronizes the synchronization signal with the dot clock.

(Operation) The horizontal synchronization signal and the vertical synchronization signal are delayed in synchronization with the dot clock by the first and second flip-flops. (Embodiment) An embodiment of the present invention will be described below with reference to the drawings. Explain in detail.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this figure, 1 is an A/D converter that A/D converts the composite video signal according to the dot clock, 2 is a sync signal separation circuit that extracts the sync signal included in the composite video signal, and 3 is the sync signal separation circuit 2 that extracts the sync signal. A horizontal synchronizing signal generation circuit generates a horizontal synchronizing signal from the output synchronizing signal; 4 a vertical synchronizing signal generating circuit generating a vertical synchronizing signal from the synchronizing signal extracted by the synchronizing signal separation circuit 2; and 5 a counter control signal. 6 is a delay clock generation counter that generates a delayed clock; 7 is a flip-flop that delays the horizontal synchronization signal C4 and the vertical synchronization signal in synchronization with the clock generated by the delay clock counter 6; 8 is a horizontal synchronization signal synchronized with the dot clock, !
This is a flip-flop that generates a vertical synchronization signal.

FIG. 2 is a time chart showing the operating state of the apparatus shown in FIG.

The operation of the apparatus of the present invention will be described below with reference to FIGS. 1 and 2.

A composite video signal Vt supplied from the outside is sent to an A/D converter 1 and a synchronization signal separation circuit 2. Composite video signal @v■
is converted into digital data DA consisting of video data and blanking data by A/D conversion@1. Also,
A synchronization signal S is extracted by a synchronization signal separation circuit 2. This synchronization signal S is generated by the horizontal synchronization signal generation circuit 3 as a horizontal synchronization signal @
H with vertical synchronization signal generation circuit 4! Delay time tc+dlJ5 and t at this time, which are converted into f vertical synchronization signal ■
pd2 is a delay that changes depending on temperature and voltage. In addition to this, the synchronous signal S is generated by the counter control signal generator 5, which generates the counter υtW signal Q synchronized with the falling edge of the synchronous signal @S.
is converted to The delayed clock generation counter 6 is a counter II[! A frequency-divided clock Q1 is created from the signal Q and the dot clock DC. This frequency-divided clock Q1 is delayed by two dot clocks in synchronization with the falling edge of the synchronization signal @S. And Flip 70 Tsubu 7 is horizontal turn Meishin @H, 11! In response to the M synchronization signal V and the frequency divided clock Q1, a horizontal synchronization signal @H' delayed by a delay time tod1 and a direct synchronization signal @V delayed by a delay time tDd2 are generated. Additionally, the flip-flop 8 outputs a delayed horizontal synchronizing signal H' and a delayed vertical @11 signal v'
and dot clock OC, dot clock DC
Horizontal synchronization signal II S and f delayed in synchronization with
! ^Generates synchronization signal vS. This horizontal synchronous signal @H8
The vertical synchronization signal @vS is not affected by temperature or voltage and can always maintain constant timing with the dot clock DC.

Note that it is possible to control the delay time by selecting the divided clock Q1 of the counter.

For example, horizontal synchronization signal delay Lodl, vertical synchronization signal delay tE) (Even if there are several clocks of 12, if a divided clock Q1 larger than this clock is selected, the obtained timing is always constant.

(Effects of the Invention) As described in detail above, in the present invention, a synchronization signal having a delay time longer than the delay time caused by differences in elements, temperature, and voltage changes is generated. As a result, FJi image signal processing 1 makes it possible to obtain a synchronization signal that is reliably synchronized with video data! Stomach can be realized.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms of various parts during operation of the present invention, and FIG. 3 is a configuration diagram showing the configuration of a conventional video signal processing device. Figure 6 1...A/D converter 2...Synchronization signal separation circuit 3.
...Horizontal synchronization signal generation circuit 4 ...Vertical synchronization signal generation circuit 5 ...Counter III 1ml signal generation section 6 ...Delay clock generation circuit 7.8 ...Flip 70 tube

Claims (1)

[Scope of Claims] A/D conversion means for A/D converting an externally applied composite video signal based on an externally applied dot clock; and a synchronization signal for extracting a synchronization signal from the externally applied composite video signal. separating means; synchronizing signal generating means for generating a horizontal synchronizing signal and a vertical synchronizing signal from the synchronizing signal extracted by the synchronizing signal separating means; and generating a counter control signal synchronized with the synchronizing signal from the periodic signal separating circuit. Counter control signal generation means; delay clock generation means for generating a clock for delaying the horizontal synchronization signal and the vertical synchronization signal; and a first flip-flop for delaying the horizontal periodic signal and the vertical synchronization signal by the delay clock. and a second flip-flop that synchronizes the horizontal synchronization signal and vertical synchronization signal delayed by the first flip-flop with a dot clock.