JPH026662Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field This invention relates to the improvement of ALC (automatic level control) circuits, and is particularly concerned with the improvement of ALC (automatic level control) circuits, which have particularly excellent characteristics and are easy to integrate into ICs (integrated circuits). Regarding.

(b) Prior art When converting a signal with varying amplitude into a signal with a constant level, as in the recording circuit of a tape recorder,
Usually an ALC circuit is used, but as an ALC circuit,
For example, there is one shown in FIG. In FIG. 1, an input signal applied to an input terminal 1 is applied to an input terminal of an amplifier circuit 4 via a resistor 2 and a capacitor 3, and after being amplified by the amplifier circuit 4,
It is led out to an output terminal 6 via an output capacitor 5. At that time, a part of the signal led out to the output terminal 6 is branched, rectified by a diode 7, smoothed by a capacitor 8, and then applied to the base of the first transistor 9. The emitter current of the first transistor 9 changes according to the signal applied to the base, and is supplied to the base of the second transistor 10, so that the collector current of the second transistor 10 also changes depending on the signal applied to the base. 1 transistor 9
It will change depending on the signal applied to the base of.

Now, suppose that the input signal is gradually increased from zero until it reaches a predetermined value V ₁ , as shown in Figure 4.
The first and second transistors 9 and 10 are not turned on, the input signal is amplified according to the amplification factor K of the amplifier circuit 4, and an output signal amplified by K times is generated at the output terminal 6. Thus, when the input signal level reaches said V ₁ , the first and second transistors 9 and 10 are turned on, and the input signal is bypassed by the collector-emitter path of the second transistor 10. Since the amount of bypass by the second transistor 10 increases as the input signal level increases, the output signal level remains approximately constant in the range where the input signal level is _V1 or higher, as shown in FIG. It is maintained.

Incidentally, in the case of the ALC circuit shown in FIG. 1, the output signal level is determined by the amplification factor of the amplifier circuit 4 and the operation start voltage of the second transistor 10. Therefore, when it is desired to change the output signal level, the amplification factor of the amplifier circuit 4 is usually changed. However, the amplification factor of the amplifier circuit 4 is related to the SN ratio (signal-to-noise ratio), THD (total harmonic distortion), frequency characteristics, etc., and when the amplification factor is changed, each of the above characteristics changes. This is not desirable because it causes Also,
Since the rectifier diode 7 must be externally connected with each capacitor, the ALC circuit shown in Figure 1 is
The circuit was not suitable for IC implementation.

(c) Purpose of the invention This invention was created in view of the above points.
ALC that can freely vary the level at which the ALC circuit starts operating, has excellent transient characteristics, and is easy to integrate into an IC.
The purpose is to provide a circuit.

(d) Structure of the invention The ALC circuit according to the invention includes a first amplifier circuit that amplifies an input signal, a second amplifier circuit that amplifies an output signal of the first amplifier circuit, and an output signal of the first amplifier circuit. and an output signal of the second amplifier circuit, and generates a first output signal corresponding to the difference between the two output signals and a second output signal having an opposite phase to the first output signal; a first charging circuit that charges the capacitor according to the output signal; a second charging circuit that charges the capacitor according to the second output signal; and a second charging circuit that adjusts the level of the input signal according to the terminal voltage of the capacitor. and an adjustment circuit.

(E) Embodiment Figure 2 is a circuit diagram showing an embodiment of the present invention.
11 is an input terminal to which an input signal is applied; 12 is a first amplifier circuit that amplifies the input signal applied to the input terminal 11; 13 is an output terminal from which the output signal of the first amplifier circuit 12 is derived; 14 a second amplifier circuit that further amplifies the output signal of the first amplifier circuit 12;
15 is a comparison circuit that compares the output signal of the first amplifier circuit 12 and the output signal of the second amplifier circuit 14; 16 is a first charging transistor to which the first output signal of the comparison circuit 15 is applied; 17 is a second output signal having an opposite phase to the first output signal of the comparison circuit 15;
a second charging transistor to which an output signal is applied to its base; 18 a smoothing capacitor charged by the collector currents of the first and second charging transistors 16 and 17; and 20 is a second transistor that turns on in response to the first transistor 19 and bypasses the input signal by its collector-emitter path.

Next, the operation will be explained. When no input signal is applied, the first and second amplifier circuits 12
No output signal is generated at the output terminals 1 and 14, and the positive and negative input terminals of the comparison circuit 15 are at the same voltage. Therefore, no output signal is generated at the output terminal of the comparison circuit 15. At that time, the bases of the first and second charging transistors 16 and 17 are connected to the first charging transistors 16 and 17.
A predetermined DC bias voltage is applied so that the second charging transistors 16 and 17 are not turned on. Therefore, the capacitor 18 is not charged, and the first and second transistors 19 and 20 remain off.

Now, if a small level input signal is applied to the input terminal 11, the input signal is applied to the first amplifier circuit 1.
2, and further amplified by the second amplification circuit 14. Since the second amplifier circuit 14 includes the feedback resistors 21 and 22 and has a negative feedback amplifier circuit configuration, the amplification factor of the second amplifier circuit 14 is the same as that of the feedback resistors 21 and 22. It is set by the ratio of The amplification factor of the first amplifier circuit 12 is
k ₁ and the amplification factor of the second amplifier circuit 14 is k ₂ , the output signals v ₀₁ and v ₀₂ of the first and second amplifier circuits 12 and 14 are respectively v ₀₁ =k ₁ v _i . ...(1) v ₀₂ = k ₁ k ₂ v _i ...(2) (however, v _i is the input signal). The output signal v ₀₁ of the first amplifier circuit 12 is
output terminal 13 and comparator circuit 1.
5 is applied to the negative input terminal of the second amplifier circuit 1.
The output signal v ₀₂ of No. 5 is applied to the positive input terminal of the comparison circuit 15 and compared in level. Then, an output signal corresponding to the level difference between the two output signals is obtained at the output terminal of the comparison circuit 15. A first output signal of the comparison circuit 15 is applied to the base of the first charging transistor 16 , and a second output signal of the comparison circuit 15 having a phase opposite to the first output signal is applied to the base of the second charging transistor 17 . applied. Therefore, the first output signal v ₀₃ and the second output signal
v ₀₄ becomes v ₀₃ = k ₁ v _i (k ₂ -1) ... (3) v ₀₄ = k ₁ v _i (1 - k ₂ ) ... (4), respectively. If the amplification factor of the second amplifier circuit 14 is 1 or more, the first
The output signal v ₀₃ is positive, the second output signal v ₀₄ is negative,
In the negative half cycle of the input signal, the first output signal v ₀₃ becomes negative and the second output signal v ₀₄ becomes positive. Therefore, when the input signal is positive, the second charging transistor 1
7 turns on and charges the capacitor 18, and when the input signal is negative, the first charging transistor 17 turns on and charges the capacitor 18. Therefore, the capacitor 18 is charged by both the positive and negative half cycles of the input signal, and the DC voltage obtained at one end of the capacitor 18 is stable with a low ripple rate.

As the comparison circuit 15, for example, one shown in FIG. 3 is used. In FIG. 3, 23 is a negative input terminal to which the output signal of the first amplifier circuit 12 of FIG. 2 is applied, 24 is a positive input terminal to which the output signal of the second amplifier circuit 14 of FIG. 2 is applied, and 25 A first differential transistor 26 whose base is connected to the negative input terminal 23, a second differential transistor 27 whose base is connected to the positive input terminal 24, and the first and second differential transistors 26 and A first differential circuit 29 includes a first current inverting circuit 28 connected between the collectors of the transistor 27; a third differential transistor 30 having a base connected to the negative input terminal 23;
A second differential circuit including a fourth differential transistor 31 whose base is connected to the positive input terminal 24, and a second current inversion circuit 32 connected between the collectors of the third and fourth transistors 30 and 31. , 33
is a constant current transistor connected to the common emitters of the first to fourth differential transistors 26 to 31;
16 is a first charging transistor whose base is connected to the collector of the third differential transistor 30, and 17 is a second charging transistor whose base is connected to the collector of the second differential transistor 27.

Therefore, in the positive half cycle of the input signal v _i , the signal v ₀₂ applied to the positive input terminal 24 is more positive than the signal v ₀₁ applied to the negative input terminal 23, so the second differential transistor 27 becomes larger than the collector current of the first differential transistor 26, the base current of the second charging transistor 17 flows to the second differential transistor 27 due to the action of the first current inversion circuit 28, and the 2 charging transistor 17 is turned on and its collector current is generated. At that time, the collector current of the third differential transistor 30 is
Since the collector current of the first charging transistor 16 is smaller than the collector current of the first charging transistor 16, the base current of the first charging transistor 16 does not flow and the second
Charging transistor 16 is off. input signal
In the negative half cycle of v _i , the negative input terminal 23
Since the signal v ₀₁ applied to the positive input terminal 24 is more positive than the signal v ₀₂ applied to the positive input terminal 24, the collector current of the third differential transistor 30 becomes larger than the collector current of the fourth differential transistor 31. , 1st
The base current of charging transistor 16 flows and turns on. At that time, the second charging transistor 17 is activated by the same operation as during the positive half cycle of the input signal _vi .
is off. Therefore, an output current corresponding to the level of the input signal v _i is obtained at the output point 34 during both positive and negative cycles of the input signal v _i , and this output current is used to charge the capacitor 18. .

Returning to FIG. 2 again, while the level of the input signal is small, the collector currents of the first and second charging transistors 16 and 17 are also small, and the capacitor 1
8 terminal voltage does not rise much. Therefore, the first
and the second transistors 19 and 20 are not turned on,
ALC operation is not performed. As the level of the input signal increases, the collector currents of the first and second charging transistors 16 and 17 also increase, and the terminal voltage of the capacitor 18 also increases. Then, when the level of the input signal becomes V ₁ , the capacitor 18
The terminal voltage of 2V _BE (however, V _BE is the first and second
The rising voltage between the base and emitter of the transistors 19 and 20 is reached, the first and second transistors 19 and 20 are turned on, and the input signal begins to be bypassed by the collector-emitter path of the second transistor 20, resulting in ALC operation. is started. Since the amount of input signal bypass by the second transistor 20 depends on the terminal voltage of the capacitor 18, it ultimately depends on the level of the input signal. Therefore, the signal applied to the input terminal of the first amplifier circuit 12 is always constant, and the signal applied to the input terminal of the first amplifier circuit 12 is always constant.
The level of the output signal obtained in step 3 is also constant. The solid line A in FIG. 5 shows the relationship between the input signal applied to the input terminal 11 and the output signal obtained at the output terminal 13. The output signal is applied to the ALC circuit until the input signal level reaches _V1. does not operate, the input signal level increases in proportion to the input signal.
After reaching V ₁ , it remains at a constant level due to the action of the ALC circuit.

The operation start level of the ALC circuit can be easily changed by simply changing the amplification factor of the second amplifier circuit 14. As mentioned earlier, the second amplifier circuit 14
is configured as a negative feedback type, so the negative feedback resistor 2
The amplification factor of the second amplifier circuit 14 can be changed by simply changing the ratio of 1 and 22 and changing the amount of negative feedback. If the amplification factor of the second amplifier circuit 14 is increased, the operation start level of the ALC circuit is lowered, and the fifth
As shown by the dashed line (b) in the figure, the ALC circuit starts operating at an input signal level _V2 lower than _V1 . Also,
If the amplification factor of the second amplifier circuit 14 is made small, the ALC circuit starts operating at an input signal level _V3 higher than _V1 , as shown by the two-dot chain line C in FIG. Since the second amplifier circuit 14 is not inserted into the main signal path between the input terminal 11 and the output terminal 13, even if the amplification factor of the second amplifier circuit 14 is changed, Unlike the conventional example, various characteristics do not deteriorate.

(f) Effects of the invention As stated above, according to the invention, there are no negative effects.
It is possible to provide an ALC circuit that can vary the operation start level of the ALC circuit. Additionally, since there is no need to add an external rectifier diode, it is possible to provide an ALC circuit suitable for IC implementation. Furthermore, according to the present invention, since the charging circuit operates in both positive and negative cycles of the input signal, the ripple rate can be greatly improved and the transient characteristics can be improved. Furthermore, according to the present invention, ALC operation can be performed regardless of load impedance.
We can provide an ALC circuit that is stable against power supply voltage fluctuations. As in the embodiment, if the charging circuit is configured with a PNP transistor and the collector current is used to charge the capacitor, the output impedance to the capacitor can be increased. For equipment requiring the capacitor, the first
The second transistor and the like can be shared, and ALC can be performed on both amplifiers at the same time.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional ALC circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, Fig. 3 is a circuit diagram showing an example of the comparison circuit, and Fig. 4 is a circuit diagram showing an example of the comparison circuit.
FIG. 5 is a characteristic diagram showing the input/output relationship of the ALC circuit, and FIG. 5 is a characteristic diagram showing the input/output relationship of the present invention. Explanation of main drawing numbers, 12...First amplifier circuit, 14
...Second amplifier circuit, 15...Comparison circuit, 16,1
7...Charging transistor, 18...Capacitor,
19,20...transistor.

Claims (1)

[Scope of utility model registration request] An ALC circuit for generating an output signal of a constant level in response to an input signal whose level changes, the circuit comprising a first amplifier circuit that amplifies the input signal, and a second amplifier circuit that amplifies the output signal of the first amplifier circuit. A second amplifier circuit compares the output signal of the first amplifier circuit and the output signal of the second amplifier circuit, and outputs a first output signal according to the difference between the two output signals and a second output signal that is in opposite phase to the first output signal. a comparison circuit that generates two output signals; a first charging circuit that charges the capacitor according to the first output signal; a second charging circuit that charges the capacitor according to the second output signal; an adjustment circuit that adjusts the level of the input signal according to the terminal voltage, and an adjustment circuit that is connected to the output terminal of the first amplifier circuit.
In addition to obtaining an output signal subjected to ALC, the ALC is performed in accordance with the amplification factor of the second amplifier circuit.
An ALC circuit characterized in that the operation start level of the circuit can be varied.