JPH0266667A - Parallel computing element - Google Patents

Abstract

PURPOSE:To decrease the overall scale of a circuit by adding an instruction decoder to each module, using the input signal instruction as a module number writing instruction, and inputting the data on the input signal to each module as a module number to be given to each module to set and rewrite the module number. CONSTITUTION:It is supposed that each module number register 4 is initialized at '0000'. Under such conditions, the module number of an input signal IN is designated as '0000' and a module number writing instruction is defined together with the data inputted to a module 10 as a module number. Then the module number '0000' of the signal IN is compared with the memory module number '0000' received from the register 4. Then a comparator 2 outputs a coincidence signal when the coincidence is obtained between both numbers '0000'. Thus an instruction decoder 3 decodes the instruction of the signal IN. This decoded instruction is equal to the module number writing instruction and therefore the data '0001' of the signal IN is written into the register 4. Then the module number of the module 10 is rewritten.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a parallel processing arithmetic unit, and in particular, a plurality of modules are connected in series, a module number for identification is set for each of these modules, and the module number is used to identify each module. The present invention relates to a parallel processing arithmetic unit configured to specify a module to be processed.

[Conventional technology]

Conventionally, this type of parallel processing arithmetic unit has, as shown in FIG. 2, an input data control section 1 that temporarily holds and outputs an input signal IN consisting of a module number, an instruction, and data;
A comparator 2 compares the memory module number from the module number register 4A with the module number of the output signal of the input data control section 1 and outputs a match signal when they match, and a comparator 2 that outputs a match signal when the stored module number from the module number register 4A and the module number of the output signal of the input data control section 1 match, and a comparator 2 that outputs a match signal when input data IN is input. A module number register that outputs the storage module number that is in the output signal and is reset when the reset signal R3 is active and writes and stores the module number of the output signal of the input data control section 1; A calculation unit 5 executes and performs arithmetic processing on the output signal of the control unit 1, and outputs the output signal of the calculation unit 5 when a match signal is output, and outputs the output signal of the input data control unit 1 when a match signal is not output. A plurality of modules 30 and 40 each having an output data control unit 6 that outputs the data as it is to the next stage.
were connected in series.

Further, each module 30.40 is provided with a module number setting section 50.60 for setting the module number of these modules 30.40,
By activating the reset signal R3, the module number setting sections 50 and 60 output the module number, and the module number is written into the module number register 4A via the input data control section 1. Specific circuit examples of these module number setting sections 50 and 60 are shown in FIGS. 3(a) and 3(b).

Incidentally, FIG. 4 shows a data format diagram of the input signal IN applied to this parallel processing arithmetic unit.

[Problem to be solved by the invention]

In the conventional parallel processing arithmetic unit described above, in order to set the module number for specifying the module (30, 40) that processes the input signal IN, each module 30.40 is set for each module 30.40. Since the configuration includes the module number setting sections 50 and 60 provided outside, there is a drawback that the entire circuit increases.

An object of the present invention is to provide a parallel processing arithmetic unit that can reduce the size of the entire circuit.

[Means to solve the problem]

The parallel processing arithmetic unit of the present invention includes an input data control unit that temporarily holds and outputs an input signal including a module number instruction and data, and a module number and storage module that the output signal of the input data control unit has. a comparator that outputs a match signal when the numbers match; and a comparator that outputs a match signal when the match signal is output, decodes the command of the output signal of the input data control section, and reads the module number when this command is a module number write command. a command decoder that outputs a write signal; and a command decoder that outputs the stored storage module number each time the input signal is input, and writes the data of the output signal of the input data control section by the module number write signal. a module number register for storing; a calculation unit for executing and calculating the output signal of the input data control unit when the coincidence signal is output; and an operation unit for executing the output signal of the calculation unit when the coincidence signal is output. and an output data control section that outputs the output signal of the input data control section as it is when the coincidence signal is not output.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Modules 10 and 20 each include an input data control section 1 that temporarily holds and outputs an input signal IN consisting of a module number, command, and data, and a module number and module number that the output signal of this input data control section 1 has. a comparator 2 that compares the storage module number from the register 4 and outputs a match signal when they match; and a comparator 2
a command decoder 3 which decodes the command of the output signal of the input data control unit 1 when a match signal is output from the input data controller 1, and outputs a module number write signal when this command is a module number write command; The module number register 4 outputs the stored memory module number each time the module number is input, and the module number register 4 writes and stores the data of the output signal of the input data control section 1 in response to the module number write signal, and a match signal is output. When a matching signal is output, a calculation unit 5 executes and performs arithmetic processing on the output signal of the input data control unit 1, and when a matching signal is output, the output signal of the calculation unit 5 is output, and when a matching signal is not output, it performs input data control. The output control section 6 outputs the output signal of the section 1 as it is, and the output control section 6 is connected in series with each other.

Next, the operation of this embodiment will be explained.

When rewriting the setting of the module number, first, the module number register 4 of each module 10.20 is uniformly initialized using the reset signal R3.

It is now assumed that each module number register 4 has been initialized to 0000'', and in this state the input signal I
The module number of N is specified as '0000'', the command is set as a module number write command, and data is input to the module 10 as a module number to be assigned to the module 10 (for example, ``0001'').

The module 10 compares the module number "o o o o'" of this input signal IN with the storage module number "o o o o" from the module number register 4, and since they match, a match signal is sent from the comparator 2. is output.

Based on this match signal, the instruction decoder 3 decodes the instruction of the input signal IN, and since this instruction is a module number write instruction, it writes the data "'OO01" of the input signal IN to the module number register 4, and writes the data "'OO01" of the input signal IN to the module 10.
module number is rewritten.

Next, to write the module number of module 20,
The module number of the input signal IN is "0000", the command is a module number write command, and the module number to assign data to module 2o (for example, '0010')
input into module 10 as .

The module 10 has the module number "o" of the input signal IN.
o o o” and the storage module number from the module number register 4 of this module 10.

001'', and since they do not match, the input signal IN is directly transmitted to the module 20 via the output data control section 6.

The module 20 receives the module signal "" o o o o" of the input signal IN transmitted thereto and the storage module number "" from the module number register 4 of this module 20.
Since they match, the command decoder 3 decodes the command of the input signal IN and writes the data "0010°" of the input signal IN to the module number register 4 of this module 20. be included.

In this way, the module number of each module 10.20 can be set and rewritten.

In this way, by providing the instruction decoder 3 in each module (10, 20), the stored contents of the module number register 4 of each module (10, 20) can be rewritten by the input signal IN. This eliminates the need for a module number setting section for each module outside the circuit, and the size of the entire circuit can be reduced.

〔Effect of the invention〕

As explained above, the present invention provides a command decoder in each module, uses the command of the input signal as a module number write command, and inputs the data of the input signal to each module as a module number to be assigned to each module. By adopting a configuration in which settings are rewritten, there is no need for a module number setting section, which was conventionally required for each module outside the module, and there is an effect that the entire circuit can be made smaller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a conventional parallel processing arithmetic unit, and FIGS. 3(a) and 3(b) are shown in FIG. FIG. 4 is a circuit diagram showing an example of a specific circuit of the module number setting section of the parallel processing arithmetic unit shown in FIG. 2, and FIG. 4 is a data format diagram of an input signal applied to the parallel processing arithmetic unit shown in FIG. 1... Input data control unit, 2... Comparator, 3...
Instruction decoder, 4, 4A...Module number register, 5...Arithmetic unit, 6...Output data control unit, 7...
・Module number generator, 8... Clocked buffer, 10.20, 30.40... Module, 50°6
0...Module number setting section. Agent: Susumu Uchihara, patent attorney, 3m! f) 4 times

Claims (1)

[Claims] An input data control unit that temporarily holds and outputs an input signal including a module number, command, and data; and a match signal when the module number of the output signal of this input data control unit and the storage module number match. and an instruction decoder that decodes the command of the output signal of the input data control section when the coincidence signal is output, and outputs a module number write signal when the command is a module number write command. and a module number register that outputs the stored storage module number each time the input signal is input, and writes and stores data of the output signal of the input data control section in response to the module number write signal; an arithmetic unit that executes and performs arithmetic processing on the output signal of the input data control unit when a match signal is output; and an arithmetic unit that outputs an output signal of the arithmetic unit when the match signal is output, and the match signal is not output. A parallel processing arithmetic unit comprising a plurality of modules each including an output data control unit that outputs the output signal of the input data control unit as it is.