JPH0478931A - Designated word interruption generating system - Google Patents

Abstract

PURPOSE:To cope with a high speed operation and simultaneous read-out of plural instruction words by providing an interruption information holding part in a storage device, and also, providing an interruption information setting means thereto, and an interruption information bus for connecting the interruption information setting means and a processor. CONSTITUTION:A storage device 12 is provided with a storage word holding part 122 for storing an instruction word, and an interruption information holding part 121 for holding interruption information of at least one bit, and an interruption information setting means 16 sets the interruption information to the interruption information holding part 121 in the storage device 12. Subsequently, an interruption information bus 14 writes the interruption information set by the interruption information setting means 16 into the interruption information holding part 121 in the storage device 12, and also, reads out the interruption information from its interruption information holding part 121 and supplies it to an external interruption terminal 111 of a processor 11. In such a way, it is possible to cope with the processor for executing read-out of an instruction word at a high speed, and also, the processor for executing simultaneous read- out of plural instruction words.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a software development environment for an information processing device, and particularly to a specified word interrupt generation method.

[Conventional technology]

Conventionally, in this type of specified word interrupt generation method, for example, the second
As shown in the figure, the address in the storage device 23 of a command word (hereinafter referred to as a designated word) designated to generate an interrupt is set by the interrupt address setting means 24 via the interrupt address hash 28 and the interrupt address setting signal line 29. When the processor 21 reads the specified word to the storage device 23 via the address bus 26 and data bus 27 to execute the specified word, the address comparator 22 registers the specified word in the interrupt address register 25 in advance. The address is compared with the contents of the interrupt address register 25, and if they match, an interrupt is generated from the external interrupt terminal 211 to the processor 21.

Incidentally, in recent years, as the speed of processors has increased, the time for successive instruction words and the read interval have been shortened, and processes that read a plurality of instruction words simultaneously have also come to be used.

[Problem to be solved by the invention]

In the conventional specified word interrupt generation method described above, it was necessary to compare the specified word address preliminarily set in the interrupt address register 25 by the interrupt address setting means 24 and the address on the address bus 26 point by point.
There is a drawback that it becomes difficult to cope with the speed-up of the process and the readout time and readout interval of seven instruction words.

Also, a process that reads multiple instruction words at the same time.

In most cases, only the address corresponding to the first word of the instruction word is output, so if you try to generate an interrupt by comparing the addresses of the instruction word, multiple addresses will be output by sequential addition starting from the first address. The disadvantage is that it becomes increasingly difficult to accommodate the readout times and readout intervals of faster processes.

In view of the above-mentioned points, an object of the present invention is to enable generation of an interrupt at a specified word with a relatively simple hardware configuration, to provide a processor that reads an instruction word at high speed, and to read a plurality of instruction words simultaneously. The purpose of the present invention is to provide a specified word interrupt generation method that can also be used with processors.

[Means to solve the problem]

The specified word interrupt generation method of the present invention includes a processor having an external interrupt terminal and a storage device for storing instruction words,
In the information processing device in which the processor sequentially executes instruction words stored in this storage device, the memory comprises a memory word holding section for storing instruction words and an interrupt information holding section for holding at least 1 bit of interrupt information. an interrupt information setting means for setting interrupt information in an interrupt information holding section in the storage device; and an interrupt information setting means for setting interrupt information in an interrupt information holding section in the storage device; and an interrupt information bus that reads interrupt information from an interrupt information holding section within the device and supplies it to an external interrupt terminal of the processor.

[Effect]

In the specified word interrupt generation method of the present invention, the storage device includes a storage word holding section for storing instruction words and an interrupt information holding section for holding at least l bits of interrupt information, and the interrupt information setting means is provided in the storage device. The interrupt information bus writes the interrupt information set by the interrupt information setting means to the interrupt information holding section in the storage device, and also reads the interrupt information from the interrupt information holding section in the storage device. Read and supply to the external interrupt pin of the processor.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing the configuration of an information processing apparatus to which a specified word interrupt generation method according to an embodiment of the present invention is applied. This information processing device is an example in which an interrupt information holding unit 121 that holds 1-bit interrupt information for each instruction word stored in a memory word holding unit 122 is added to the storage device 12, and an external interrupt terminal 111; a storage device 12 including an interrupt information holding section 121 and a memory word holding section 122; a data bus 13 connecting the processor 11 and the storage device 12; Storage device 12 and interrupt information setting means 1
6 and the processor 11.
．． It is composed of an address bus 15 that connects the storage device 12 and the interrupt information setting means 16, and an interrupt information setting means 16.

It is assumed that the processor 11 generates an interrupt when the value "1" is input to the external interrupt terminal 111.

The interrupt information holding unit 121 is configured to read and write interrupt information via the interrupt information bus 14 . It is assumed that the interrupt information in the interrupt information holding unit 121 has a value of "0" as an initial value.

Next, the operation of the I-order categorical interrupt generation method of this embodiment configured as described above will be explained.

First, using the interrupt information setting means 16, the address of the designated word in the storage device 12 is given to the address bus 15, and at the same time, interrupt information with a value "1" is sent to the interrupt information lot 14.
give to

Then, interrupt information with a value of "1" is set in the interrupt information holding section 121 corresponding to the specified word of the corresponding address held in the memory word holding section 122 of the storage device 12.

Now, for example, as shown in FIG.
” is set.

Next, the processor 11 executes the memory word holding unit 1 of the storage device 12.
The instruction word or data stored in 22 is transferred to address bus 1.
5, and reads and executes a command word or data via the data bus 13.

For example, as shown in FIG. 3, the processor 11 sends the address (n-1) to the storage device 12 via the address bus 15 in order to execute the instruction word at the address (n-1), and the instruction word "1nstn- 1” to the data bus 13,
At the same time, the interrupt information value of address (n-1) is “O”.
” is read out to the interrupt information lot 14, but since the value of the interrupt information read out to the interrupt information no.\x4 is “0”, the processor 11 does not generate an interrupt.

Next, in order to execute the instruction word at address n, processor 1] transfers address n to storage device ]2 via address bus 15.
When the instruction word "I n S L n" is read out onto the data bus 13, the value "1" of the interrupt information at address n is read out into the interrupt information node 14 at the same time.

The value of the interrupt information read to the interrupt information bus 14 is “1”
” is manually input to the external interrupt terminal 111 and the processor 1
1 generates an interrupt.

By the way, if the processor 11 is a processor that reads two instruction words at the same time, for example, as shown in FIG.
An interrupt information logical sum circuit 124 is introduced into the storage device 12, and the interrupt information corresponding to two instruction words, for example, the interrupt information of address (n-1) and address n, is logically summed and then output to the interrupt information bus 14. By inputting the interrupt signal to the external interrupt terminal 111 of the processor 11 via the .

The same applies even if the processor 11 reads three or more instruction words at the same time.

In the above embodiment, the case where the interrupt information is 1 bit is explained as an example, but the present invention can be similarly applied even if the interrupt information is 2 bits or more to avoid logical malfunctions. It goes without saying that it is possible.

〔Effect of the invention〕

As explained above, the present invention provides at least one
In addition to providing an interrupt information holding section that holds interrupt information of bits, an interrupt information setting means for setting interrupt information in the interrupt information holding section and an interrupt information lot connected to the interrupt information setting means and an external interrupt terminal of the processor are provided. As a result, it is possible to generate an interrupt at a specified word with a relatively simple hardware configuration, and there is no need to compare the addresses of instruction words one by one. This has the effect of being able to accommodate the reading interval.

Also, a process that reads multiple instruction words at the same time.

This has the effect that it is possible to easily set the occurrence of interrupts even for applications.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing the configuration of an information processing device to which a specified word interrupt generation method according to an embodiment of the present invention is applied, and FIG. 2 is a circuit block diagram showing an example of a conventional specified word interrupt generation method. , FIG. 3 is a diagram showing an example of storage in the storage device in FIG. 1, and FIG. 4 is a diagram illustrating the configuration in the storage device when two instructions are read simultaneously in the specified word interrupt generation method of this embodiment. be. In the figure, 1 l · 12 · 13 · 14 · 15 · Processor, Storage device, · Data bus, · Interrupt information bus, · Address bus, · Interrupt information setting means, · External interrupt terminal, · Interrupt information holding unit,・Memory word holding unit, ・OR circuit.

Claims (1)

[Scope of Claims] An information processing device comprising a processor having an external interrupt terminal and a storage device for storing instruction words, wherein the processor sequentially executes instruction words stored in the storage device, the information processing device storing the instruction words. the storage device comprising a memory word storage section for storing interrupt information and an interrupt information storage section for storing at least one bit of interrupt information; an interrupt information setting means for setting interrupt information in the interrupt information storage section in the storage device; an interrupt information bus for writing the interrupt information set by the information setting means into an interrupt information holding section in the storage device, reading the interrupt information from the interrupt information holding section in the storage device, and supplying the read interrupt information to an external interrupt terminal of the processor; A specified word interrupt generation method characterized by having the following.