JPH0267437U - - Google Patents
Info
- Publication number
- JPH0267437U JPH0267437U JP14611888U JP14611888U JPH0267437U JP H0267437 U JPH0267437 U JP H0267437U JP 14611888 U JP14611888 U JP 14611888U JP 14611888 U JP14611888 U JP 14611888U JP H0267437 U JPH0267437 U JP H0267437U
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory
- store
- register
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Hardware Redundancy (AREA)
Description
第1図はこの考案の一実施例による電子計算機
を示す構成図、第2図はこの考案の一実施例によ
る動作の詳細を示すフローチヤート、第3図は従
来の電子計算機の代表的な2つのタイプを示す構
成図である。
第1図において1はCPU、2はROM、3は
RAM、4はバス、5は搭載プログラム、6はR
AM上のワークエリア、7はスペアエリア、8は
セグメントプログラム、13はロード命令、15
はストア命令である。また、第1図〜第4図にお
いて、同一符号は同一または相当部分を示す。
Fig. 1 is a configuration diagram showing an electronic computer according to an embodiment of this invention, Fig. 2 is a flowchart showing details of operation according to an embodiment of this invention, and Fig. 3 is a typical two-dimensional diagram of a conventional electronic computer. FIG. 2 is a configuration diagram showing two types. In Figure 1, 1 is the CPU, 2 is the ROM, 3 is the RAM, 4 is the bus, 5 is the installed program, and 6 is the R
Work area on AM, 7 is spare area, 8 is segment program, 13 is load instruction, 15
is a store instruction. Moreover, in FIGS. 1 to 4, the same reference numerals indicate the same or corresponding parts.
Claims (1)
み出し専用メモリと、データの読み書き可能メモ
リによつて構成される電子計算機において上記中
央処理装置のレジスタの中に、データをロードす
るアドレスの基準となるデータとデータをストア
するアドレスの基準となるデータを格納すること
のできるレジスタを有し、上記データの読み書き
可能メモリの中に、可変パラメータや中間データ
の収納場所とスタツク待避場所を二重系として格
納することのできるメモリエリアを備え、上記デ
ータの読み出し専用メモリの中に、上記データの
読み書き可能メモリのデータをチエツクし、前記
データをロードするアドレスの基準となるデータ
レジスタとデータをストアするアドレスの基準と
なるデータレジスタを書き換えるプログラムを格
納することのできるメモリエリアを備えた電子計
算機。 In an electronic computer consisting of a central processing unit that controls processing, a data read-only memory, and a data readable/writable memory, it serves as the reference address for loading data into the register of the central processing unit. It has a register that can store data and data that is the standard of the address to store the data, and the above data read/write memory has a dual system of storage locations for variable parameters and intermediate data and a stack save location. A data register that is a reference address for checking the data in the read/write memory and loading the data, and an address for storing the data, in a read-only memory that has a memory area that can store the data. An electronic computer equipped with a memory area that can store a program that rewrites the data register that serves as the standard for the computer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14611888U JPH0267437U (en) | 1988-11-09 | 1988-11-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14611888U JPH0267437U (en) | 1988-11-09 | 1988-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0267437U true JPH0267437U (en) | 1990-05-22 |
Family
ID=31415310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14611888U Pending JPH0267437U (en) | 1988-11-09 | 1988-11-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0267437U (en) |
-
1988
- 1988-11-09 JP JP14611888U patent/JPH0267437U/ja active Pending
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