JPH03113404U - - Google Patents
Info
- Publication number
- JPH03113404U JPH03113404U JP2278390U JP2278390U JPH03113404U JP H03113404 U JPH03113404 U JP H03113404U JP 2278390 U JP2278390 U JP 2278390U JP 2278390 U JP2278390 U JP 2278390U JP H03113404 U JPH03113404 U JP H03113404U
- Authority
- JP
- Japan
- Prior art keywords
- program
- control device
- numerical control
- processing section
- number storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Numerical Control (AREA)
Description
第１図〜第４図はこの考案の一実施例に係り、
第１図は数値制御装置のブロツク図、第２図は動
作を示すフローチヤート、第３図ａはサブプログ
ラムを使用した加工プログラムの例を示す図、第
３図ｂはこのプログラムを運転したときの、各々
のレジスタの内容を示す図、第４図ａは運転中に
戻し操作をし再開スタートが出来るプログラムの
例を示す図、第４図ｂはその場合の各々のレジス
タの内容を示す図、第５図は従来の数値制御装置
のブロツク図、第６図は従来の数値制御装置の動
作を示すフローチヤートである。
図において、１は加工プログラムメモリ、２は
プログラムサーチ処理部、３はプログラム読み込
み処理部、４は先読バツフア、５はデータ処理部
、９は表示処理部、１２はプログラム番号記憶レ
ジスタ、１３はシーケンス番号記憶レジスタ、１
４はブロツク個数記憶レジスタ、１５はシーケン
ス番号個数記憶レジスタである。なお、図中、同
一符号は同一、または相当部分を示す。
Figures 1 to 4 relate to an embodiment of this invention,
Figure 1 is a block diagram of the numerical control device, Figure 2 is a flowchart showing the operation, Figure 3a is a diagram showing an example of a machining program using subprograms, and Figure 3b is when this program is operated. Fig. 4a is a diagram showing an example of a program that can perform a return operation during operation and restart, and Fig. 4b is a diagram showing the contents of each register in that case. , FIG. 5 is a block diagram of a conventional numerical control device, and FIG. 6 is a flowchart showing the operation of the conventional numerical control device. In the figure, 1 is a machining program memory, 2 is a program search processing section, 3 is a program reading processing section, 4 is a prefetch buffer, 5 is a data processing section, 9 is a display processing section, 12 is a program number storage register, and 13 is a Sequence number storage register, 1
4 is a block number storage register, and 15 is a sequence number storage register. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
序を記憶する手段を備えた数値制御装置。 A numerical control device equipped with means for storing the execution order of programs during program operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2278390U JPH03113404U (en) | 1990-03-07 | 1990-03-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2278390U JPH03113404U (en) | 1990-03-07 | 1990-03-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03113404U true JPH03113404U (en) | 1991-11-20 |
Family
ID=31525792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2278390U Pending JPH03113404U (en) | 1990-03-07 | 1990-03-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03113404U (en) |
-
1990
- 1990-03-07 JP JP2278390U patent/JPH03113404U/ja active Pending
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